CODEWITHSUNDEEP
vhdl
Darth_Sygnious
Darth_Sygnious

Reputation: 558

Non-recommended latches generated in VHDL

As part of a school project where we do genetics algorithm, I am programming something called "crossover core" in VHDL. This core is supposed to take in two 64-bit input "parents" and the two outputs "children" should contain parts from both inputs.

The starting point for this crossover is based on a value from an input random_number, where the 6 bit-value detemines the bit-number for where to start the crossover.

For instance, if the value from the random_number is 7 (in base 10), and the inputs are only 0's on one, and only 1's on the other, then the output should be something like this:

000.....00011111111 and 111.....11100000000

(crossover start at bit number 7)

This is the VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity crossover_core_split is
    generic (
        N : integer := 64;
        R : integer := 6
    );
    port (
        random_number : in  STD_LOGIC_VECTOR(R-1 downto 0);
        parent1       : in  STD_LOGIC_VECTOR(N-1 downto 0);
        parent2       : in  STD_LOGIC_VECTOR(N-1 downto 0);
        child1        : out STD_LOGIC_VECTOR(N-1 downto 0);
        child2        : out STD_LOGIC_VECTOR(N-1 downto 0)
    );
end crossover_core_split;

architecture Behavioral of crossover_core_split is
        signal split : INTEGER := 0; 
begin

    split <= TO_INTEGER(UNSIGNED(random_number));

    child1 <= parent1(N-1 downto split+1) & parent2(split downto 0);
    child2 <= parent2(N-1 downto split+1) & parent1(split downto 0);

end Behavioral;

The code is written and compiled in Xilinx ISE Project Navigator 12.4. I have tested this in ModelSim, and verified that it works. However, there is an issues with latches, and I get these warnings:

WARNING:Xst:737 - Found 1-bit latch for signal <child1<62>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <child1<61>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.  
ETC ETC ETC...

WARNING:Xst:1336 -  (*) More than 100% of Device resources are used

A total of 128 latches are generated, but appearantly they are not recommended. Any advices in how to avoid latches, or at least reduce them?

Upvotes: 1

Views: 846

Answers (1)

Scola
Scola

Reputation: 66

This code is not well suited for synthesis: the length of the sub-vectors should not vary and maybe this is the reason for the latches. For me the best solution is to create a mask from the random value: you can do that in many way (it's typically a binary to thermometric conversion). As example (it's not the optimal one):

process(random_number)
begin
  for k in 0 to 63 loop
    if k <= to_integer(unsigned(random_number)) then
      mask(k) <= '1';
    else
      mask(k) <= '0';
    end if;
  end loop;
end process;

then once you have the mask value you can simply write:

child1 <= (mask and parent1) or ((not mask) and parent2);
child2 <= (mask and parent2) or ((not mask) and parent1);

Upvotes: 3

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