CODEWITHSUNDEEP
verilogflip-flop
jeebface
jeebface

Reputation: 841

No output from a pattern matching module

The objective is to write structural Verilog code for a circuit that has two inputs, w1 and w2, and an output, q. The circuit compares the input sequences of w1 and w2. If w1 and w2 match for 4 consecutive clock pulses, q should be 1; otherwise it should remain at 0.

Example:

w1 = 0100111010010
w2 = 0000110010010
q  = 0000010000111

I've drawn a state diagram and a state table and concluded that I need 3 D flip flops for this circuit. I then wrote K-maps for the inputs of each D-FF. However, when I wrote the code, the resulting waveform unexpectedly looks like this:

http://i.imgur.com/BwRgP7j.png

Here is my code:

module PatternMatch2(q, w1, w2, clk, rst);
    output  q;
    input   w1, w2, clk, rst;

    DF DF1(y1, yBar1, Y1, clk, rst),
       DF2(y2, yBar2, Y2, clk, rst),
       DF3(y3, yBar3, Y3, clk, rst);

    and and0(Y1, nI, yBar3, yBar1),
        and1(Y2In1, nI, yBar2, y1),
        and2(Y2In2, nI, y2, yBar1),
        and3(Y3In1, nI, y3),
        and4(Y3In2, nI, y2, y1),
        and5(q, y3, yBar2, yBar1);

            xor xor0(i, w1, w2);        


    or or0(Y2, Y2In1, Y2In2),
       or1(Y3, Y2In1, Y2In3);

    not not0(nI, i);

endmodule


// D - Flip Flop Module
module DF(q, qBar, D, clk, rst);
    input D, clk, rst;
    output q, qBar;

    reg q;

    not n1 (qBar, q);

    always@ (posedge rst or posedge clk)
    begin
    if(rst)
            q = 0;

    else
            q = D;
    end
endmodule

I'm not sure what's wrong in my code as my equations seem correct.

Upvotes: 1

Views: 1504

Answers (2)

glexey
glexey

Reputation: 811

You only need 2 FFs organized as a saturating counter with reset for such task:

  1. Create a reset signal rst=XOR(w1,w2) and connect to both FF's reset input

  2. Connect your FFs inputs (d0, d1) to outputs (q0, q1) according to a following truth table (2-bit counter with saturation): 

    q1 q0 => d1 d0
0  0  => 0  1
0  1  => 1  0
1  0  => 1  1
1  1  => 1  1

    That is: 

    d0 = OR(NOT(q0), q1)
d1 = OR(q0, q1)

  3. Your output will be: q=AND(q0, q1, NOT(rst))

Upvotes: 1

toolic
toolic

Reputation: 62037

When I compile your code, I get this warning message:

Implicit wire 'Y2In3' does not have any driver

You need to drive your or1 input appropriately.

Upvotes: 1

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