CODEWITHSUNDEEP
armoverflow
MarcL
MarcL

Reputation: 3593

how comes the overflow flag in an ARM Processor together?

how is the V (Overflow) Flag in an ARM Processor created? is it the Carry-Bit XOR the highest (31.Bit) = Negative Bit ? C XOR N ?? or is it the C - Bit and the Carry Bit from Bit 30 to 31 ?

Upvotes: 1

Views: 9104

Answers (5)

Collado
Collado

Reputation: 161

The overflow flag is there to help us catch inconsistencies with signs. As you may know, ARM microprocessors like the M3 use 2's Complement to represent negative numbers. In this representation scheme, the MSB indicates the sign of the number we are dealing with.

  • If MSB = 1 -> Negative Number
  • If MSB = 0 -> Positive Number

Then, the overflow flag is set when the result of an operation has an unexpected sign. For example, let A = 01111b = 15d and B = 00001b = 1d. Both these numbers are positive (MSB = 0), but what happens when we add them together?

A + B = 01111b + 01b = 10000b = -16d!

We see how the result has a changed sign! The overflow flag (commonly denoted as V) will be set in accordance.

Now, we can be sure the overflow flag wont be set under certain circumstances. For example, if we subtract same sign magnitudes we can get both positive and negative results, hence a change in sign is not necessarily an error. The same goes for additions with different signed operands. Then, overflow is something to look out for in additions with operands having the same sign and subtractions where the operands have a different sign.

This answer is based on the Wikipedia article on the topic: https://en.wikipedia.org/wiki/Overflow_flag

Upvotes: 3

Jake 'Alquimista' LEE
Jake 'Alquimista' LEE

Reputation: 6354

A very simple explanation : V is set if an ALU instruction with the suffix 's' alters the MSB.

a = MSB(n); //before
d = ALUs(n);
b = MSB(d); // after
V = a ^ b;

Upvotes: 1

Gautam
Gautam

Reputation: 375

Concept of overflow comes when you are working with signed numbers. ARM integer registers (processor supporting V7 instruction and lower) use 32 bits . Integer arithmetic dose not distinguish between signed numbers and unsigned numbers. Note that overflow is only possible if you are using numbers in arithmetic(say addition) which are both positive or both negative. Here is an example code 

    MOV r0,#0x40000000
    MOV r1,#0x40000000
    ADDS r3,r1,r0       ;; this will cause overflow bit to be set in NZCV flags

Note here that r0 and r1 contained positive numbers . But their sum 0x80000000 is a negative number in signed sense.32 bits are not enough to represent +0x80000000.Look at the 31st bit of the operands,if both are 0( both are positive numbers) or both are 1(both are negative numbers) and the 31st bit of result is different form the 31st bit of operands ,then a overflow has occurred.The condition could be stated as 

 ((31st bit of op1) equal to (31st bit of op2)) not equal to (31st bit of result)

Upvotes: 1

Artur
Artur

Reputation: 7257

V flag on ARM processor is indicator of last's arithmetic operation signed overflow. The flag will for example be set for the following addition 0x7FFFFFFF+1=0x80000000 (2 positive vals added but got negative)

For NEG operation V flag will be set if MSB is 1 (smallest value in U2 does not have negative value that can be represented in the same number of bits as operand). In other cases (additions, subtractions) it will be set if carry into MSB will be different than carry out of MSB.

Upvotes: 2

auselen
auselen

Reputation: 28087

I generally end up reading this page: Condition Codes 1: Condition Flags and Codes

V: (Signed) Overflow

The V flag works the same as the C flag, but for signed operations. For example, 0x7fffffff is the largest positive two's complement integer that can be represented in 32 bits, so 0x7fffffff + 0x7fffffff triggers a signed overflow, but not an unsigned overflow (or carry): the result, 0xfffffffe, is correct if interpreted as an unsigned quantity, but represents a negative value (-2) if interpreted as a signed quantity.

Upvotes: 0

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