CODEWITHSUNDEEP
inputverilogsystem-verilogtest-bench
Steven Li
Steven Li

Reputation: 19

Can anyone help me to create a Verilog testbench?

Can anyone help me create a testbench or just the input code for my following code? I'm using XILINX.

module fsmb (input rst,clk,a,
             output reg x);

parameter sta = 2'b00, stb = 2'b01, stc = 2'b10,
          std = 2'b11;

reg[1:0] st, nst;

always @(posedge clk)
begin 
    if (rst)
        st <= 2'b00;
    else
        st <= nst;
end

always @*
begin
    st = nst; x =0'b0;
    case (st)
        sta: if(a) nst = stb;
             else nst = sta;
        stb: if(a) nst = stc;
             else nst = stb; 
        stc: begin 
             if(a) nst = stc;
             else nst = std; 
             x =1'b1;
             end
        std: begin
             if(a) nst = stc;
             else nst = sta;
             x = 1'b1;
             end
        default: nst = sta;
    endcase 
end
endmodule

Upvotes: 0

Views: 3324

Answers (2)

toolic
toolic

Reputation: 62037

Testbench 101

  1. Create a new module (tb).
  2. Create a reg for each input of your DUT.
  3. Create a wire for each output of your DUT.
  4. Create an instance of your DUT.
  5. Connect your regs and wires to your DUT.
  6. Generate a clock
  7. Drive your other inputs
  8. Create checkers for your outputs (I'll leave this up to you).

Example:

module tb;

reg rst,clk,a;
wire x;

initial begin
    clk = 0;
    forever #5 clk = ~clk;
end

initial begin
    rst = 1;
    a = 0;
    #50 rst = 0;
    #50 $finish;
end

fsmb fsmb (
    .clk    (clk),
    .rst    (rst),
    .a      (a),
    .x      (x)
);

endmodule

Other simple testbench examples are provided on EDA playgound. You can sign up for a free account and look at samples such as: Published Playgounds -> D flip flop

Upvotes: 11

Thomas S.
Thomas S.

Reputation: 11

Xilinx ISE will generate a skeleton test fixture automatically. Go to menu item Project->New Source. The dialog box will ask you to "Select Source Type" click "Verilog Test Fixture" and give it a name like testbench1 and click Next. Then it will then ask you which module in your project to associate with it. Select fsmb. Click Next and Finish.

You still have to tweak the testbench like setting the initial input values, generating a clock, and lifting reset after a few clocks.

Upvotes: 1

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