CODEWITHSUNDEEP
intelcpu-cacheperf
user2609910
user2609910

Reputation: 157

performance counters for cache events on Intel Xeon

I try to use performance counters (linux perf) for Intel Xeon E5 family.

I am rather confused on the interpretation of cache misses. While L1 and LLC values are easily accessible , information for L2 had to be read from registers via the -rNNN event. But on the documentation I haven't found how the event number with the mask field is combined to give the NNN value. Only one example in perf help shows a value A8 and a mask of 01 resulting in 1a8. But what is the general rule when masking? Shouldn't it be written in the documentation or it is a standard OR function or something?

Also I haven't understood from the documentation or from other relevant topics' replies, whether LLC values measured in Xeon case are for L3 or L2. What happens when there is third level of cache in the hardware? Does the LLC still measure last level i.e. L3 events?

Has anybody cleared it out?

Upvotes: 1

Views: 692

Answers (2)

Moncef M.
Moncef M.

Reputation: 1293

"LLC" stands for Last-Level cache. Most modern Intel systems have 3 levels of cache, so on your processor, the LLC is the L3 cache.

Upvotes: 0

Milind Dumbare
Milind Dumbare

Reputation: 3234

May be you can look at the kernel and find out the event numbers for Xeon.

Here is what I found for arm v7 A8

arch/arm/kernel/perf_event_v7.c:168

[C(LL)] = {
    [C(OP_READ)] = {
        [C(RESULT_ACCESS)]      = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
        [C(RESULT_MISS)]        = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
    },

And arch/arm/kernel/perf_event_v7.c:75

ARMV7_A8_PERFCTR_L2_CACHE_ACCESS                = 0x43,
ARMV7_A8_PERFCTR_L2_CACHE_REFILL                = 0x44,

So after looking at event number 0x43 and 0x44 in ARM's TRM You can know what exactly they mean

Upvotes: 1

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