CODEWITHSUNDEEP
c#monomakefile
Generalkidd
Generalkidd

Reputation: 579

How do write a makefile for C#?

I have a simple C# program that needs to be run from the command line in Linux through mono. Here's what I have for my makefile so far. It's based off of a C++ makefile I found for another program. I tried modifying it to work with my C# program but it says certain source files could not be found. 

.PHONY : build view clean

build : test
@# do nothing

test : test.o
gmcs test test.o

test.o : test.cs
gmcs test.cs

view :
@\less test.cs

clean :
-\rm *.exe
-\rm test

I've never worked with makefiles before so I don't really know what I'm doing wrong. There's only one file in my entire project and that's just test.cs. The final goal of this is to be able to run the program by typing in the command line:

./test

And it should clean up the .exe files generated too.

Upvotes: 7

Views: 16393

Answers (3)

bzim
bzim

Reputation: 1070

I'm using a pretty simple model of Makefile in my projects. (PS: I'm compiling using mono on GNU/Linux, but it is pretty easy to change the configurations (read my comments))

#change this to the name of the Main class file, without file extension
MAIN_FILE = App/Program

#change this to the depth of the project folders
#if needed, add a prefix for a common project folder
CSHARP_SOURCE_FILES = $(wildcard */*/*.cs */*.cs *.cs)

#add needed flags to the compilerCSHARP_FLAGS = -out:$(EXECUTABLE)
CSHARP_FLAGS = -out:$(EXECUTABLE)

#change to the environment compiler
CSHARP_COMPILER = mcs

#if needed, change the executable file
EXECUTABLE = $(MAIN_FILE).exe

#if needed, change the remove command according to your system
RM_CMD = -rm -f $(EXECUTABLE)



all: $(EXECUTABLE)

$(EXECUTABLE): $(CSHARP_SOURCE_FILES)
    @ $(CSHARP_COMPILER) $(CSHARP_SOURCE_FILES) $(CSHARP_FLAGS)
    @ echo compiling...

run: all
    ./$(EXECUTABLE)

clean:
    @ $(RM_CMD)

remake:
    @ $(MAKE) clean
    @ $(MAKE)

Upvotes: 1

guyincognito
guyincognito

Reputation: 203

I put together a really simple Mono Makefile that works for me:

.PHONY: test.cs

all: run

test.exe: test.cs
    @gmcs test.cs 

clean:
    @rm -f test.exe

run: test.exe
    @mono test.exe

This has the nice property that if you just type 'make' it will re-compile and execute test.cs.

Upvotes: 2

elyashiv
elyashiv

Reputation: 3691

In order to answer the question, I will explain more about makefiles:
when you have a statement like that:

test: test.o
    gmcs test test.o

it means: in order to build target test, you will need target test.o and to run the command gmcs test test.o.

when you type in the command line make target it will try to build target by the rules you wrote in the makefile. So, in our case, when you execute make test the program will try to build test, see it needs to build test.o before, find this rule:

test.o: test.cs
    gmcs test.cs

find the file test.cs, run gmcs test.cs, then go back to the previous target, and run gmcs test test.o now, you don't have test nor test.o in your directory, so the command reports an error.

What got you confused (and i could just guess about this) is the c++ make file. In c++ you first create object files (.o in linux, .obj in windows), then link them together. I'm not sure, but the command in the c++ makefile you have for a .o target was with the -c flag - a flag that tells gcc to just compile. In your case the program was completely compiled after the first command.

So - the makefile you are looking for is the following:

PHONY : build view clean

build : test
@# do nothing

test: test.cs
    gmcs test.cs -out:test

view :
@\less test.cs

clean :
-\rm *.exe
-\rm test

that will create a file named test, and you could run it with mono test. if you want to omit the mono you can create a script file:

#! /bin/bash

mono test

don't forget to change the permissions to allow you to execute it!

Upvotes: 1

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