Verilog Parsing Using ANTLR grammar

Question

I am trying to create a parser in Java (using Netbeans) which can take in any arbitrary Verilog file as an input and generate a netlist containing gates as the output. The netlist does not have to be optimized.

I have the ANTLR grammar file https://github.com/antlr/grammarsv4/blob/master/verilog/Verilog2001.g4

However, I am not really quite sure how to integrate it into my Java program.

For instance, if I had the following Verilog file as input,

module and3(output out, input in1, in2,in3);
  reg r_out;
  assign out = r_out;
  always@(in1, in2, in3)
    begin
      case({in3,in2,in1})
        000: out = 0;
        001: out = 1;
        010: out = 1;
        011: out = 1;
        100: out = 0;
        101: out = 1;
        110: out = 0;
        111: out = 1;
        default: out = 0;
      endcase
    end
endmodule

I would like to identify the names of the input and output ports as well as their size. I would also like to identify the always block as well as the case statement block and each assignment within the Case Statement.

So my doubts are:

1) How do I integrate this into my java program

2) How do I use this Verilog Grammar file and read the Verilog code mentioned above to recognize inputs, outputs, case statements, assign statements.

Thanks

Answer 1

I have recently solved a similar task. I started creating an IntelliJ plugin for Verilog using the same grammar file for ANTLR. Currently, it parses Verilog files successfully and does some highlight/completion etc.

Here is my code https://github.com/MrTsepa/jetbrains-verilog-plugin

Firstly I generate ANTLR AST tree with some ANTLR tools (embedded in ANTLR plugin for Idea) and then adapt this tree to IntelliJ's AST format (PSI tree) via ANTLR adapter