CODEWITHSUNDEEP
vhdl
jason
jason

Reputation: 7164

No function declarations for operator + error in VHDL

In this piece of code I get this error for the line with +

function func (bv1 : in bit_vector; bv2 : in integer) return bit_vector is

    variable temp : natural := 2**bv2;
    variable result : bit_vector(1 to 32);
  begin
    report "asd" & natural'image(temp);
     result <= bv1 + temp; // this line causes the error
    return result;
  end func;

The error is :

No function declarations for operator +

How can I solve this? I also get a similar error for "=" as well.

Upvotes: 1

Views: 9293

Answers (3)

Martin Thompson
Martin Thompson

Reputation: 16792

Don't use bit_vectors (or std_logic_vectors, really) for anything you want to do arithmetic on.

Use the ieee.numeric_std library and then declare your signals (or whatever) to be of type signed ot unsigned depending on what type of vector you want. (Or of course, you can just use integers and the subtypes of that)

Upvotes: 4

Morten Zilmer
Morten Zilmer

Reputation: 15924

Some initial problems with the code are that VHDL comments markup is --, not //, and assign to result variable must use :=, since <= is for assign to signal.

Then, the reason for the error:

No function declarations for operator +

is that VHDL is a strong typed language, so it is not possible just to add a natural type and a bit_vector type, as attempted in result <= bv1 + temp. Instead you need to use the package numeric_bit_unsigned, and for example convert temp to bit_vector using function to_bitvector before adding.

Resulting code can then be:

library ieee;
use ieee.numeric_bit_unsigned.all;
...
function func (bv1 : in bit_vector; bv2 : in integer) return bit_vector is
  variable temp   : natural := 2**bv2;
  variable result : bit_vector(1 to 32);
begin
  report "asd" & natural'image(temp);
  result := bv1 + to_bitvector(temp, result'length);  -- this line causes the error
  return result;
end func;

You should check that the length is enough to handle the required values.

However, instead of using bit_vector type, you may consider the std_logic_vector (depending on the design), since the std_logic_vector has additional values that may reveal design problem in simulation.

Upvotes: 1

Sebastian
Sebastian

Reputation: 8154

It's because you try to add a natural to a bit_vector which does not work because they are of different types. So you'll have to use a converter, e.g. as shown here within one of the functions. The other method is to stick to all the same types, but that isn't always possible.

Upvotes: 1

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