CODEWITHSUNDEEP
system-verilog
adir
adir

Reputation: 1287

Systemverilog assignment - logic array to byte array

I'm trying to assignment logic l_data[31:0]; to byte data[];.

data = l_data; is not legal SystemVerilog assignment. How can it be done?

Upvotes: 1

Views: 5438

Answers (1)

dave_59
dave_59

Reputation: 42673

Use a bit-stream cast (section 6.24.3 of the IEEE Std 1800-2012 LRM). You will need to create a typedef for the cast, but it is a good idea to use typedefs for all your variable declarations anyways.

typedef byte unsigned dynamic_byte_array_t[];
typedef logic fixed_logic_array_t[31:0];

dynamic_byte_array_t data;
fixed_logic_array_t l_data;

data = dynamic_byte_array_t'(l_data);

A couple of notes:

  1. Be careful using byte, it is signed by default.
  2. I add a _t suffix to all my type basic names,
  3. I suggest using more meaningful type names than what I have used here.
  4. The bit-stream cast has one specific order to move bits-left-to-right. Use the streaming operator if you need more complex bit ordering (Section 11.4.14)

Upvotes: 5

Related Questions