Cannot evaluate genvar conditional expression

Question

ı am doing this work over here http://web.cs.hacettepe.edu.tr/~onderefe/bbm231/2013-2014%20Guz%20Proje.pdf
and getting these errors:

microislemci.v:10: error: Cannot evaluate genvar conditional expression: 
    (opcode)==(4'd0)
microislemci.v:10: error: Cannot evaluate genvar conditional expression: 
    (opcode)==(4'd0)
2 error(s) during elaboration.

any ideas?

module mikroislemci(data1,data2,opcode,data_out,flag);
input  [7:0] data1;
input  [7:0] data2;
input  [3:0] opcode;
output [7:0] data_out;
output [4:0] flag;
wire   [8:0] tmp;
wire   [7:0] tmp1;

 if(opcode == 4'b0000)
 begin 
    if (data1==data2)
      begin
        assign flag[0]=1;
      end
    else
      begin
        assign tmp = data1+data2;
        assign data_out=tmp [7:0];
            assign flag[2]=tmp [8];
      end
 end
else if (opcode==4'b0001)
  begin
    if (data1==data2)
      begin
        assign flag[0]=1;
      end
    if(data1>data2)
      begin
            assign data_out=data1-data2;
      end
    else
      begin 
                assign data_out=data2-data1;
        assign  flag[1]=1;
      end

  end 
 else if (opcode==4'b0010)
   begin
    assign data_out[0]=data1[0] & data2[0];
    assign data_out[1]=data1[1] & data2[1];
    assign data_out[2]=data1[2] & data2[2];
    assign data_out[3]=data1[3] & data2[3];
    assign data_out[4]=data1[4] & data2[4];
    assign data_out[5]=data1[5] & data2[5];
    assign data_out[6]=data1[6] & data2[6];
    assign data_out[7]=data1[7] & data2[7];

  end
else if (opcode==4'b0011)
  begin
    assign data_out[0]=data1[0] || data2[0];
    assign data_out[1]=data1[1] || data2[1];
    assign data_out[2]=data1[2] || data2[2];
    assign data_out[3]=data1[3] || data2[3];
    assign data_out[4]=data1[4] || data2[4];
    assign data_out[5]=data1[5] || data2[5];
    assign data_out[6]=data1[6] || data2[6];
    assign data_out[7]=data1[7] || data2[7];

  end
else if (opcode==4'b0100)
  begin
    assign data_out[0]=data1[0] ^ data2[0];
    assign data_out[1]=data1[1] ^ data2[1];
    assign data_out[2]=data1[2] ^ data2[2];
    assign data_out[3]=data1[3] ^ data2[3];
    assign data_out[4]=data1[4] ^ data2[4];
    assign data_out[5]=data1[5] ^ data2[5];
    assign data_out[6]=data1[6] ^ data2[6];
    assign data_out[7]=data1[7] ^ data2[7];

  end
else if (opcode==4'b0101)
  begin
    assign data_out[0]= !(data1[0]);
    assign data_out[1]= !(data1[1]);
    assign data_out[2]= !(data1[2]);
    assign data_out[3]= !(data1[3]);
    assign data_out[4]= !(data1[4]);
    assign data_out[5]= !(data1[5]);
    assign data_out[6]= !(data1[6]);
    assign data_out[7]= !(data1[7]);

  end
else if (opcode==4'b0110)
  begin
    if(data1==data2)
      begin
                assign flag[0]=1;
      end
    else if(data1<data2)
      begin
        assign flag[4]=0;
      end
    else if(data1>data2)
      begin
        assign flag[4]=1;
      end

  end
else if (opcode==4'b0111)
  begin
     assign data_out=data1<<data2;
  end
else if (opcode==4'b1000)
  begin
     assign data_out=data1>>data2;
  end

 else
 begin
  display("you entered wrong opcode try again");
 end


endmodule

Answer 1

You are not writing correct verilog. if statements need to go inside a procedural block (like always), they cannot exist alone in a module.

Around your whole if statement, place this combinational procedural block:

always @* begin //<--- new line
  if(opcode == 4'b0000)
  ...
  else if 
  ...
  end
end             //<--- new line

Also inside a procedural block, you don't need the keyword assign (it means something else here), so remove all the assigns from all the lines inside the block. Instead of assign a=b;, just write a=b;.

You will also need to change your wire types to reg type to assign them in a procedural block.