CODEWITHSUNDEEP
linuxcachingmemory
ecem
ecem

Reputation: 3614

L1 Data Cache Configuration

We are currently working on level 1 cache misses and according to the results we gathered with the help of PAPI I started to think that we may be doing something wrong.

I am currently running the tests on my laptop with Intel(R) Core(TM) i3-2370M CPU @ 2.40GHz. According to the specs, L1 data cache has 32 KB size with 8-way set associativity and a line has 64 bytes. Therefore we concluded that it has 64 sets with each set having 8 lines.

Given a 32 bit memory address, we think that it has the following structure for the placement in L1 cache:

TAG |  line id  |   set id   |  line offset
     ----------  ------------  -------------
       3 bits       6 bits       6 bits

Is this assumption true?

Upvotes: 1

Views: 122

Answers (1)

twalberg
twalberg

Reputation: 62389

Not exactly. What "8-way" means is that a particular line of memory may be in any one of 8 different cache lines. So your cache does consist of essentially 8 different sets of 64 lines each, but your tag (assuming a 64-bit system here) is actually 52 bits (in theory, assuming all 64 bits are implemented, which is not uniformly true), with 6 bits to identify the line id, and then 6 bits of offset. The cache circuits will look up that 52-bit tag in all 8 different sets (usually in parallel, or as close to it as possible). There are no bits allocated from the address to specify the "way"-ness...

Upvotes: 1

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