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cunixmakefile
Zhivago
Zhivago

Reputation: 337

How to write a Makefile to compile a simple C program

Compile the following program 

#include <stdio.h>
int main(void)
{
   printf ("Hello from your first program!\n");
   return 0;
}

a)-by using file of type Makefile

b)-the executable will be named Hello

"Please help to do an exercise. I know how to do it in CodeBlocks, but I don't know what Makefile is and how to write it in Linux. I compiled it using command "gcc filename.c" and subsequently "./a.out" but I still don't understand what the Makefile is. Is it a sort of shell script, an instruction? How would a Makefile for this task exactly look? Thanks in advance :) "

Upvotes: 21

Views: 104448

Answers (4)

Aaron Digulla
Aaron Digulla

Reputation: 328770

A makefile is a recipe for computers with instructions how to perform certain tasks and with dependencies between those tasks.

In the simple form, it looks like so:

a.out: filename.c
        gcc filename.c

Read: "To build a.out from filename.c, run the command gcc filename.c. If a.out is newer than filename.c, then don't do anything"

Note: The first character in the gcc line must be a tab (Makefiles are whitespace sensitive)

Upvotes: 5

vishesh
vishesh

Reputation: 101

before going for makefile you have to know what's it and why we need it

What is Makefile?

Makefile is a script written in a certain prescribed syntax which helps to build the target output (normally, one or more executables) from source files by compilation and linking. In simple words, makefile will compile your source code in simple & fast way. Why we need Makefile?

=> Large projects can contain multiple source files which are dependent in one another or arranged in hierarchical manner for example, in order to compile file A, you have to first compile B; in order to compile B, you have to first compile C; and so on.

=> Make is a solution to these problems. It can be used to compile whole project in well arranged manner and generate your target according to your make rule(which we will discuss later) by entering single command that is make.

=> An important feature is that when a project is recompiled after a few changes, it will recompile only those files which are changed, and any other files that are dependent on it. This saves a lot of time.

=> For a large project, when a few changes are made to the source, manually recompiling the entire project each time is tedious, error-prone and time-consuming.

Here is nice link for it :How to write first makefile

Upvotes: 9

Jayesh Bhoi
Jayesh Bhoi

Reputation: 25915

This is your simple make file for hello program.

CC      = gcc
CFLAGS  = -g
RM      = rm -f


default: all

all: Hello

Hello: Hello.c
    $(CC) $(CFLAGS) -o Hello Hello.c

clean veryclean:
    $(RM) Hello

Suppose you have two makefiles in one directory named makefile.m1 and makefile.m2 and if you want build both make file then please use following commands

make -f makefile.m1
make -f makefile.m2

or use single Makefile that contains:

m1:
  make -f makefile.m1

m2:
  make -f makefile.m2

and use make m1 or make m2

Now lets clear your doubt about name of make file must not require Makefile

You can name makefile whatever you want. suppose i would like to give name myfirstmakefile.mk. To use it later you need to tell make what makefile you want. Use -f option for this:

make -f myfirstmakefile.mk

And again extantion .mk is also not manadatory you can use whatever you want but never forgot to use -f option.

so may this help make sense to you.

Upvotes: 28

Jens
Jens

Reputation: 72747

A makefile is a recipe for the make utility how to create some file (called a target) from some other files (called dependencies) using a set of commands run by the shell. A makefile typically looks like this:

target: dependency [...]
        command1
        command2

Try running man make for details.

Now for your task, really there is no need for a Makefile, since make has built-in rules that know how to compile a simple program. All you need to do is place your C source in a file named after the executable name (Hello) and with a .c extension, i.e. Hello.c.

Then a simple

$ make Hello
cc     Hello.c   -o Hello

does everything. If you want to use gcc instead of cc, you can run

$ rm Hello
$ make CC=gcc Hello
gcc     Hello.c   -o Hello

If you tell your instructor/teacher/prof that an empty makefile is all you need since you know the built-in rules do the right thing, you'll get some extra credit and maybe your instructor has learnt something new :-) If you are asked for a reference, you could quote the relevant parts of the make manual, or, do it like a pro, quote from the POSIX Standard for the make utility, section Default Rules.

Upvotes: 12

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