CODEWITHSUNDEEP
vhdlxilinx
Cactus
Cactus

Reputation: 27626

Connecting ports by name in VHDL, UCF-style

I have a VHDL entity defined like this:

entity RealEntity is
  port(
    CLK_50MHZ: in std_logic;
    LED : out std_logic_vector(3 downto 0)
    );
end RealEntity;

If I also have UCF entries for LED<0>..LED<3> and CLK_50MHZ, then I can compile this entity directly.

However, I don't actually have a 50 MHz clock on my board, so I have to use a clock manager chip. I'm using Xilinx tools for this which has a wizard to add a DCM core, and then I wrap it in another VHDL entity for easy use:

entity dcm is
  port(
    CLK_32MHZ: in std_logic;
    CLK_50MHZ: out std_logic
    );
end dcm;

where CLK_32MHZ is something that actually exists in my UCF.

To connect these two, I am currently using a third entity to be used as my toplevel one:

entity main is
  port(
    CLK_32MHZ : in  std_logic;
    LED       : out std_logic_vector(3 downto 0)
    );
end main;

architecture arch of main is
  signal CLK_50MHZ : std_logic;

  component dcm
    port(
      CLK_32MHZ : in  std_logic;
      CLK_50MHZ : out std_logic
      );
  end component;

  component RealEntity
    port(CLK_50MHZ : in  std_logic;
         LED       : out std_logic_vector(3 downto 0)
         );
  end component;

begin
  inst_dcm : dcm
    port map(
      CLK_32MHZ => CLK_32MHZ,
      CLK_50MHZ => CLK_50MHZ
      );

  inst_RealEntity : RealEntity
    port map(
      CLK_50MHZ => CLK_50MHZ,
      LED       => LED
      );

end arch;

As you can see, this third entity is 100% boilerplate. My question is, is it possible to avoid writing this main entity, and instead just use RealEntity and dcm directly, and connect the two CLK_50MHZ ports by virtue of them sharing their name, basically emulating CLK_50MHZ being present in my UCF file?

Upvotes: 3

Views: 1088

Answers (2)

Martin Thompson
Martin Thompson

Reputation: 16792

Somehow you have to tell the tools how to wire up your DCM and your real entity. Your "boilerplate" top-level entity is what achieves that. You can't do it in the UCF file as it doesn't allow you to create connections, just attach various attributes to the connections that you have made.

So your problem then becomes one of what tools exist to enable you to "wire things up" as efficiently as possible. Brian has enumerated some options for you there...

You can reduce your boilerplate by using direct instantiation. Remove your component declarations and then do:

inst_RealEntity : entity work.RealEntity
    port map(
      CLK_50MHZ => CLK_50MHZ,
      LED       => LED
      );

Upvotes: 3

user1818839
user1818839

Reputation:

I don't know of any such facility in the language itself, and I would rather not see such "implicit connections" as being too fragile. Often the top level is not quite boilerplate but an adaptor layer, and such implicit connections would then lead to too many unintended mistakes.

There are tools to simplify creating the boilerplate top level : Mentor Graphics "Renoir" cough "HDL Designer" is one such tool that automatically creates it from a block diagram : which you can think of as compilable documentation... Expensive though.

I have never personally got along with Emacs, but I would expect it to get pretty close to creating the boilerplate for you : and there, I would encourage it to create default "implicit connections" for you, as saving you work and still giving you final control.

Sigasi has also been mentioned and is well worth a look.

And I would be interested in hearing about other tools to accomplish the same.

Upvotes: 3

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