user3227168
Reputation: 5
higher frequency clock generation in RTL
I need develope synthesizable custom verilog code for generating a higher frequency clock from low frequency clock i.e from 50 MHz clock i need to generate 100 MHZ clock . kindly help how to do the same.
Upvotes: 0
Views: 920
Answers (1)
Morten Zilmer
Reputation: 15924
A pure Verilog solution is not stable, so dedicated FPGA resources must be used.
Please see this previous answer; it applies to Verilog also, even through tagged VHDL.
Upvotes: 2
Related Questions
- Using PLL to generate clock signal superior to 400Mhz on MAX10 FPGA
- Defining generated clock as synchronous in RTL simulation
- Generate 1000 MHz clock in VHDL from 100 MHz
- Clock Conversion for RTL Verilog (FPGA) Synthesizable Code
- How to Map the clock in RTL synthesis with memory?
- Alternative method for creating low clock frequencies in VHDL
- Setting FPGA clock frequency using Timing Constraints
- Generate frequency on FPGA
- How to implement clock frequency multiplier using VHDL
- high frequency from low frequency clock