CODEWITHSUNDEEP
system-verilog
user3314064
user3314064

Reputation: 11

System verilog: Passing parameters to package

I have to update few enumerated data types which are declared inside a package and mine is a special scenario where the size of my enum data type will vary with a parameter value. I have to make that parameter value somehow visible to the package.

I am aware that packages are not the components that can be instantiated. Hence I cannot pass the parameters directly.

Could anyone help me in getting my requirement done with help of some tweaks.

PS: The requirement is related to TB

Upvotes: 1

Views: 4546

Answers (1)

Tudor Timi
Tudor Timi

Reputation: 7573

What we usually do for types of lengths that have to be parameterized is use defines instead of package parameters:

package some_package_pkg;
  `ifndef MAX_DATA_WIDTH
  `define MAX_DATA_WIDTH 32

  typedef [`MAX_DATA_WIDTH-1:0] bit some_type;
  ...
endpackage

By default, MAX_DATA_WIDTH is 32, but if we need a bigger width, we just pass the define from the command line. For Incisive it is something like:

irun -D MAX_DATA_WIDTH=64 some_package_pkg.sv

If you want to retrofit an existing package that uses a parameter you could do:

package some_param_package_pkg;
   parameter P_MAX_DATA_WIDTH = `MAX_DATA_WIDTH; // just add this line

   typedef [P_MAX_DATA_WIDTH-1:0] bit some_type; // all declaration are unchanged
endpackage

Upvotes: 3

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