CODEWITHSUNDEEP
vhdl
Rogger Fernandes
Rogger Fernandes

Reputation: 73

What is the difference between these 2 vhdl codes

What is the difference between these 2 vhdl codes?

First:

library IEEE;
use IEEE.Std_Logic_1164.all;

entity mux4 is
port(
   in1, in2, in3, in4 : in std_logic;
   ctrl: in std_logic_vector(1 downto 0);
   sai: out std_logic
   );
end mux4;

architecture mux_bhv of mux4 is
begin
    process(in1, in2, in3, in4, ctrl)
        begin case ctrl is
            when "00" => sai <= in1;
            when "01" => sai <= in2;
            when "10" => sai <= in3;
            when "11" => sai <= in4;
            when others => null;
        end case;
    end process;
end mux_bhv;

Second:

library IEEE; 
use IEEE.Std_Logic_1164.all; 

entity mux4x1 is 
    port(w, x, y, z: in std_logic_vector(7 downto 0); 
        s: in std_logic_vector(1 downto 0); 
        m: out std_logic_vector(7 downto 0) 
        ); 
end mux4x1; 

architecture circuito of mux4x1 is 
begin 
    m <= w when s = "00" else 
        x when s = "01" else 
        y when s = "10" else 
        z; 
end circuito;

Upvotes: 0

Views: 191

Answers (3)

user3324521
user3324521

Reputation: 13

as stated above "In the first mux, the output sai is not updated when ctrl contains a non-zero/one value."
because of this lack of assignment most of the software tools will create an intermediate (and probably undesired) latch. Something that is not happening in the second code, where all possible values are assigned.

Upvotes: 0

user3273575
user3273575

Reputation: 16

One other slight difference, besides std_logic vs std_logic_vector is in simulation: the second mux's output m is set to z when s is "11" and when s contains any of the non-zero/one values (i.e. Z, X, H, L, ...).

In the first mux, the output sai is not updated when ctrl contains a non-zero/one value.

Again, this is only a simulation difference.

Upvotes: 0

user3300910
user3300910

Reputation: 19

For the first program:

library IEEE;
use IEEE.Std_Logic_1164.all;

entity mux4 is
port(
in1, in2, in3, in4 : in std_logic;
ctrl: in std_logic_vector(1 downto 0);
sai: out std_logic
);
end mux4;

architecture mux_bhv of mux4 is
begin
process(in1, in2, in3, in4, ctrl)
    begin case ctrl is
        when "00" => sai <= in1;
        when "01" => sai <= in2;
        when "10" => sai <= in3;
        when "11" => sai <= in4;
        when others => null;
    end case;
end process;
end mux_bhv;

You have four binary one bit input, one two bits selection line and one output. So, that is your port declaration. Then at your architecture: the use of case is for selection. So, as declared in your input, the selection line is ctrl. When it is 00 then choose the first input. If you choose ctrl "01", then you pass the second input and so on..

library IEEE; 
use IEEE.Std_Logic_1164.all; 

entity mux4x1 is 
port(w, x, y, z: in std_logic_vector(7 downto 0); 
    s: in std_logic_vector(1 downto 0); 
    m: out std_logic_vector(7 downto 0) 
    ); 
end mux4x1; 

architecture circuito of mux4x1 is 
begin 
m <= w when s = "00" else 
    x when s = "01" else 
    y when s = "10" else 
    z; 
end circuito;

The same idea 4-1 multiplixer, but here your input and output are 7-bit instead on only one bit. I hope that you get it ^_^.

Upvotes: 1

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