CODEWITHSUNDEEP
vhdlfpgahdlmodelsimintel-fpga
user3300910
user3300910

Reputation: 19

Calling a Component Inside Another Component "Port Mapping" (Illegal Statement) VHDL

I am facing a confusing problem in my program. I need in my program to port map (calling) a component. Also, inside the component, I need to do another port mapping (calling) which is illegal in VHDL. Do you have an alternative solution to this problem. Here is an example of what I meant.

Here I start my program:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity binary1 is
port( N: in std_logic;
  d: out integer);
end binary1 ;  


Architecture Behavior1 of binary1 is

Here is a component for example:

component binary_integer_1 is
port ( b1: in std_logic;
   int1: out integer);
end component;

The command for calling the component: begin s0: binary_integer_1 port map(n,d); end Behavior1 ;

Also, here is the main program:

library ieee;
use ieee.std_logic_1164.all;
entity binary_integer_1 is
port ( b1: in std_logic;
int1: out integer);
end binary_integer_1;
architecture Behavior4 of binary_integer_1 is 
begin
process(b1)
begin
if b1 = '1' then
   int1 <= 1; 
   else
   int1 <= 0;
 end if;
 end process;
 end Behavior4;

For example, if I want to do a port map inside the upper entity. I have got an illegal statement. Please, provide me with another way to do it.

Upvotes: 0

Views: 2850

Answers (1)

user1155120
user1155120

Reputation:

I did a small example of a three level design hierarchy. The entity and architecture pairs are listed from bottom to top.

entity comp1 is
    port (
        x:      in      integer;
        y:      out     integer 
    );
end entity;

architecture foo of comp1 is
begin
    y <= x after 2 ns;
end architecture;

entity comp2 is 
    port (
        a:      in  integer;
        b:      out integer
    );
end entity;

architecture fum of comp2 is
    component comp1 is
        port (
            x:      in      integer;
            y:      out     integer 
        );
    end component;

begin
INST_COMP1:
    comp1 port map (X => A, Y => B);
end architecture;

entity top is
end entity;

architecture fum of top is
     component comp2 is 
        port (
            a:      in  integer;
            b:      out integer
        );
    end component;

    signal a:   integer := 0;
    signal b:   integer;

begin
INST_COMP2:
    comp2 port map (a => a, b => b);

TEST:
    process 
    begin
        wait for 5 ns;
        a <= 1;
        wait for 5 ns;
        a <= 2;
        wait for 5 ns;
        a <= 3;
        wait for 5 ns;
        wait;
    end process;

end architecture;

ghdl -a component.vhdl

ghdl -e top

ghdl -r top --wave=top.ghw

(open top.ghw with gtkwave, setup waveform display), and:

enter image description here

So we have a top level entity top, which happens to be a test bench (no ports), it instantiates component comp2 which contains an instantiated component comp1, which provides a 2 ns delayed assigned to the output from the input.

The maximum negative value for the integer b is the left value for the integer range, and is the default, just like for std_logic the left value is 'U'; The output shows the default value until simulation time advances to an occurrence of x being assigned to y in comp1 (after 2 ns). The transition to 0 happened because of the default value for x in top.

I used integers to avoid context clauses (a library clause and a use clause). I could have used direct entity instantiation, but you showed a component declaration.

Upvotes: 1

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