CODEWITHSUNDEEP
cmakefile
Orion
Orion

Reputation: 574

Makefile error on compiling C files

My directory structure is:

Project/
    + Source/
    |    + Module_1/
    |    |    + Module_1.c
    |    |    + Module_1.h
    |    |
    |    + Module_2/
    |    |    + Module_2.c
    |    |    + Module_2.h
    |    |
    |    + MainFile.c
    |    + MainFile.h
    |
    + Makefile

My Makefile contains:

SHELL     := /bin/sh
CC        := clang
AR        := ar
CFLAGS    := -fPIC -std=c99 -O2
LDFLAGS   := -shared
ARFLAGS   := -rcs

BLDDIR    := Build
OBJDIR    := Object

SOURCES   := $(wildcard Source/**/*.c Source/*.c)
OBJECTS   := $(patsubst %.c, $(OBJDIR)/%.o, $(SOURCES))

TARGET_A  := $(BLDDIR)/MyLibrary.a
TARGET_SO := $(patsubst %.a, %.so, $(TARGET_A))


PREFIX    ?= /usr/local


# ------------------------------------------------------------------------------
.PHONY: all build clean dev distclean _dir

all: build

dev: CFLAGS := -g -Wall -Wextra -fPIC -std=c99
dev: all

build: _dir $(TARGET_A) $(TARGET_SO)
_dir:
    mkdir -p $(BLDDIR)
    mkdir -p $(OBJDIR)

$(TARGET_A) : $(OBJECTS)
    $(AR) $(ARFLAGS) %@ $(OBJECTS)
    $(AR) -s %@

$(TARGET_SO):
    $(CC) $(LDFLAGS) -o $@ $(OBJECTS)

$(OBJDIR)/%.o : %.c
    $(CC) $(CFLAGS) -c $< -o $@


clean:
    $(RM) -r $(OBJDIR) test

distclean: clean
    $(RM) -r $(BLDDIR)

I have 1 question and 1 problem with this Makefile:

  1. My problem is when I'm running this file I'm getting an error on line $(OBJDIR)/%.o : %.c and I don't know how to fix it? I tried to change it to $(OBJECTS) : %.o : %.c OR %.o : %.c and still no luck.
  2. This is my first Makefile and I was wondering if my setup in this file looks OK or I need a better strategy/rules? If so how can I improve this?

EDIT

The error I'm getting is:

make: *** No rule to make target 'Object/MainFile.c', needed by 'Object/MainFile.o'. Stop.

EDIT

As @Beta point it out in the comment, I change the file name in each module so that *.o file name be different.

Upvotes: 0

Views: 134

Answers (1)

Eric Urban
Eric Urban

Reputation: 3810

Your makefile is trying to build a C-source file. You have a dependency of each object listed as somefile.c. Based on your make file it is up a directory and in the directory Source. So change the line $(OBJDIR)/%.o : %.c to $(OBJDIR)/%.o : ../Source/%.c. With that rule it should find the .c file and then execute the command, since the dependency of the .o file exists.

Upvotes: 1

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