CODEWITHSUNDEEP
makefile
Mannix
Mannix

Reputation: 431

make is ignoring some depedencies

Here is my Makefile:

CC=gcc
CFLAGS=-Wall -std=gnu99
OBJ1=mknlrescs.o collisionsys.o csheader.o utils.o labels.o csdata.o 
OBJ2=mknrescs.o utils.o

all: mknlrescs mknrescs

mknlrescs: $(OBJ1)
$(CC) $(CFLAGS) -o $@ $<

mknrescs: $(OBJ2)
    $(CC) $(CFLAGS) -o $@ $<

%.o: %.c %.h
    $(CC) $(CFLAGS) -c $<

When I type make mknlrescs I get the following:

$ make mknlrescs
gcc -Wall -std=gnu99   -c -o mknlrescs.o mknlrescs.c
gcc -Wall -std=gnu99 -c collisionsys.c
gcc -Wall -std=gnu99 -c csheader.c
gcc -Wall -std=gnu99 -c utils.c
gcc -Wall -std=gnu99 -c labels.c
gcc -Wall -std=gnu99 -c csdata.c
gcc -Wall -std=gnu99 -o mknlrescs mknlrescs.o -lm
mknlrescs.o: In function `main':
mknlrescs.c:(.text+0x4b): undefined reference to...

And a bunch of other "undefined reference to..." errors.

The rest of the objects are not being linked. Notice it only linked the first object file. How can I correct this?

Upvotes: 0

Views: 24

Answers (1)

MadScientist
MadScientist

Reputation: 100956

The automatic variable $< stands for the first prerequisite of the rule that defined the recipe.

If you want to use ALL the prerequisites, use $^ instead.

See Automatic Variables for a full list.

Upvotes: 1

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