CODEWITHSUNDEEP
verilog
user3185902
user3185902

Reputation: 117

Verilog generate statement issue

I was trying to use the generate function in Verilog. The code compiled successfully, but it couldn't simulate. I get the following errors:

Illegal output or inout port connection for "port 'sum'".
Illegal output or inout port connection for "port 'carry'".

Could anyone tell me what am I doing wrong?

module test(input wire [2:0] a, 
        input wire [2:0] b,
        output reg [2:0] s,
        output reg [2:0] c);

genvar i;
generate 
for(i=0;i<3;i=i+1)
    adder_half inst(.sum(s[i]),.carry(c[i]),.a(a[i]),.b(b[i]));
endgenerate 

endmodule

module adder_half(
  output sum,carry,
  input a,b
    );
 xor(sum,a,b);
 and(carry,a,b);

endmodule

Upvotes: 0

Views: 556

Answers (1)

toolic
toolic

Reputation: 61987

The reg type is only used for procedural assignments, but instance connections are treated more like continuous assignments.

Remove the reg keyword from your outputs. Change:

    output reg [2:0] s,
    output reg [2:0] c);

to:

    output [2:0] s,
    output [2:0] c);

Upvotes: 3

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