CODEWITHSUNDEEP
verilog
Karthikeyan Baskaravel
Karthikeyan Baskaravel

Reputation: 5

Monitor statement verilog

Removing #2 reset after monitor statement makes the code not to work.The output just stands at 0 x. Whereas including it works fine. Why?

module counter(out,clock,reset);
input clock,reset;
wire clock,reset;
output [3:0]out;
reg [3:0]out; 
always @(posedge clock or negedge clock)
begin
if(reset)
    out<=1'b0;  
else
    out<=out+1;
end
endmodule

module tb();
reg clock,reset;
output [3:0]out;
counter c(out,clock,reset);
initial
begin
    clock=0;
    reset=1;
end
initial
begin
    $monitor("%d %d",$time,out);
    #2 reset=0;
end
always
    #1 clock=~clock;
initial
    #100 $finish;
endmodule

Upvotes: 0

Views: 981

Answers (1)

Greg
Greg

Reputation: 19104

By removing the #2 you create a race condition on reset:

initial reset = 1;
initial reset = 0;

Simulators will often have the the final value of reset the last assignment read in the compiling order. Try merging you initial blocks:

initial
begin
    $monitor("%d %d",$time,out);
    clock=0;
    reset=1;
    #2 // <-- optional (and still recommened) if you make the below change
    // @(clk) //<-- if you truely want a dual edge triggered flip-flop with synchronous reset
    reset=0;
end

Dual edge triggered flip-flop are very uncommon and many synthesizers and FPGAs do not support them. I'm guessing you are intending to have an negative edge triggered flip-flop with an active high asynchronous reset. In this case replace:

always @(posedge clock or negedge clock)

with:

always @(negedge clock or posedge reset)

Upvotes: 2

Related Questions