CODEWITHSUNDEEP
vhdlxilinx
user3529032
user3529032

Reputation: 23

How to create a test bench code for full adder?

How can I make a testbench for this full adder code. I'm a newbie and would appreciate any help.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Full_Adder is

PORT(a , b , C_In : IN STD_LOGIC; S,C_Out : OUT STD_LOGIC);

end Full_Adder;

architecture Behavioral of Full_Adder is
begin

S <= a XOR b XOR C_In;
C_Out <= (a AND b) OR (a AND C_In) OR (b AND C_In);

end Behavioral;

Upvotes: 1

Views: 5414

Answers (1)

N8TRO
N8TRO

Reputation: 3364

Here's a good reference, one of the first that came up when I googled how to write a testbench.
You should google first, give it an honest shot, then come back here with more specific questions.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Full_Adder_tb is     
end Full_Adder_tb;

architecture Behavioral of Full_Adder_tb is

   component Full_Adder is -- component declaration
   port(
      a : in std_logic;
      b : in std_logic;
      C_in : in std_logic;
      S : out std_logic;
      C_out : out std_logic
   );
   end component;

   signal a: std_logic := '0'; -- signal declarations
   signal b: std_logic := '0';
   signal C_in: std_logic := '0';
   signal S: std_logic;
   signal C_out : std_logic;

begin

   uut : Full_Adder -- component instantiation
   port map(
      a => a, -- signal mappings
      b => b,
      C_in => C_in,
      S => S,
      C_out => C_out);

process 
begin 
   wait 10 ns; -- wait time 
   a <= '0'; b <= '0'; C_in <= '1'; -- example test vector
   wait 10 ns;

   -- Other test vectors and waits here

end process;


end Behavioral;

Upvotes: 3

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