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pradeep
pradeep

Reputation: 3095

How to learn to write VHDL test benches?

I am learning VHDL along with it I want to learn to write test benches for VHDL code. Please suggest good books, resources, links that teach to write VHDL test benches?

Upvotes: 1

Views: 778

Answers (2)

VAP
VAP

Reputation: 551

See chapter 10 of "Circuit Design and Simulation with VHDL", V. Pedroni, MIT Press, 2010.

Upvotes: 0

Kevin Thibedeau
Kevin Thibedeau

Reputation: 3411

The only book I know of that specifically focuses on testbenches with VHDL is Janick Bergeron's "Writing Testbenches: Functional Verification of HDL Models" (2000, 2003). It covers both VHDL and Verilog. ISBN-10: 1402074018, ISBN-13: 978-1402074011. The ISBN of my older copy is 0-7923-7766-4. There is a paperback version as well. It is very thorough but it tends to lean toward explaining things for Verilog and then providing the VHDL equivalent. The full capability of VHDL isn't properly revealed by these types of mixed language books.

The main thing to understand with testbenches is that you can use the whole language rather than the synthesizable subset. Most instructional materials stay focused on describing logic and their testbench examples are somewhat simplistic. You should learn more about the non-synthesizable parts of the language and make an effort to understand how the simulation engine works with regard to transactions/events and how they are scheduled.

It helps to write in as high a level as possible and try not to get bogged down in low level bit twiddling if it can be avoided. You can practice this by treating VHDL as an ordinary software language, writing subprograms that carry out tasks without consideration for hardware necessities. You can then build a testbench that operates much like a software unit test. For more sophisticated testing you can progress to the use of file I/O and dynamic memory allocation to manage complex data moving in and out of the design.

Upvotes: 3

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