CODEWITHSUNDEEP
makefile
Stephen305
Stephen305

Reputation: 1097

Makefile with multiple wildcards in prerequisites

I have the following Makefile, and I am trying to simplify it. Any ideas?

PROG_NAME=a.out

all: $(PROG_NAME)
    "\nBuilt all\n"

$(PROG_NAME): build/file1.o build/file2.o build/file3.o build/file4.0
    gcc -o $@ $^

#build file1.c and file2.c which are both in ../src directory
build/file%.o: ../src/file%.c
    gcc -I ../inc -o $@ $<

#build file3.c and file4.c which are both in ../src2 directory
build/file%.o: ../src2/file%.c
    gcc -I ../inc -o $@ $<

I tried this and it does not work:

PROG_NAME=a.out

all: $(PROG_NAME)
    "\nBuilt all\n"

$(PROG_NAME): build/file1.o build/file2.o build/file3.o build/file4.0
    gcc -o $@ $^

#build ../src/file1.c, ../src/file2.c, ../src2/file3.c, and ../src2/file4.c
build/file%.o: ../src/file%.c ../src2/file%.c
    gcc -I ../inc -o $@ $<

Upvotes: 1

Views: 420

Answers (2)

Stephen305
Stephen305

Reputation: 1097

I was able to simplify it using the make variable VPATH.

http://www.gnu.org/software/make/manual/make.html#General-Search

PROG_NAME=a.out
VPATH=../src:../src2

all: $(PROG_NAME)
    "\nBuilt all\n"

$(PROG_NAME): build/file1.o build/file2.o build/file3.o build/file4.0
    gcc -o $@ $^

build/file%.o: file%.c
    gcc -I ../inc -o $@ $<

Upvotes: 1

MadScientist
MadScientist

Reputation: 100866

You cannot simplify it. The only way would be to use makefile metaprogramming to generate the rules via eval or something.

Your attempt will clearly not work, because this:

build/file%.o: ../src/file%.c ../src2/file%.c
        gcc -I ../inc -o $@ $<

says "for any target build/fileXXX.o that you want to build, you can create it by running this gcc command on the file ../src/fileXXX.c if either of the files ../src/fileXXX.c or ../src2/fileXXX.c are older than the .o". That's obviously not what you want to do.

Upvotes: 1

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