CODEWITHSUNDEEP
vhdl
alexhilton
alexhilton

Reputation: 125

How to add std_logic to an integer value

I am trying to run two 7 segments here, I have searched everywhere but could not find a satisfactory reply, how can I add 1 to a std_logic ? I tried the logic_arith library as well but nothing works. I read somewhere that i gotta use a (0 to 0) vector but umm i didn't really get that part. Here is my code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_arith.all;

entity blah is
Port ( clk : in  STD_LOGIC;
        anode: out STD_LOGIC_VECTOR (3 downto 0);
        segment: out STD_LOGIC_VECTOR (6 downto 0));
end blah;

architecture Behavioral of blah is
signal sel: STD_LOGIC;
signal r_anode: STD_LOGIC_VECTOR (3 downto 0);
begin
anode <= r_anode;
    process (clk) begin
        if (clk'event and clk = '1') then 
            sel <= sel+1;
        end if;
        end process;

    process (sel) begin
        case sel is 
                when '0' => r_anode <= "1110";
                when '1' => r_anode <= "1101";
                when others => r_anode <= "1111";
                end case;
            case r_anode is
                when "1110" =>  segment <= "0100100";
                when "1101" =>  segment <= "0010010";
                when others => segment <= "1111111";
            end case;
    end process;
    end;

And the error

 ERROR:HDLParsers:808 - "E:/Xilinx Projects/blah/blah.vhd" Line 19. + can not have such operands in this context.

Upvotes: 1

Views: 1844

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15924

The sel is only a single bit, so adding 1 is like a not sel.

However, if sel is more bits in a std_logic_vector, you can add a natural to std_logic_vector as unsigned with:

sel <= std_logic_vector(unsigned(sel) + 1);

Use only ieee.numeric_std, thus remove the ieee.std_logic_arith, since std_logic_arith is not a standard library (Synopsys proprietary).

Upvotes: 4

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