CODEWITHSUNDEEP
makefilegnu-make
dbbd
dbbd

Reputation: 894

Makefile macro to generate rules

The following makefile is an example. I'm trying to generate the rules for building targets using a defined macro.
What I get is 

make: *** No rule to make target `../x86_64/lib-reloc-debug/libstats.tar', needed by `all'.  Stop.

sources=$(wildcard $1/*.cpp)
MODE_SUFFIX=-debug
M=../x86_64/lib$(MODE_SUFFIX)
L=../x86_64/lib-reloc$(MODE_SUFFIX)
dir_c_objects=$(patsubst %.c,%.o,$(wildcard $1/*.c))
dir_cpp_objects=$(patsubst %.cpp,%.o,$(wildcard $1/*.cpp))
dir_objects=$(filter-out    $1/test%, $(call dir_c_objects, $1) $(call dir_cpp_objects, $1))
dir_objects_with_tests=$(call dir_c_objects, $1) $(call dir_cpp_objects, $1)
libobjdir=$(subst lib,obj,$(dir $1))
l_prefix=$(foreach file,$(1),$(addprefix $L/, $(file))))
TRACE=$(if $(VERBOSE),,@)
define my_make_archive
    $(eval name:=$(strip $1))
    $(eval reqs:=$2)
    $(eval L_sources:=$(call sources, $(name)))
    $(eval objects:=$(call dir_objects, $(name)))
    $(eval L_objects:=$(foreach file,$(objects),$(addprefix $L/, $(file))))
    $(eval M_objects:=$(foreach file,$(objects),$(addprefix $M/, $(file))))
    $(eval L_reqs:=$(foreach file,$(reqs),$(addprefix $L/, $(file))))
    $(eval M_reqs:=$(foreach file,$(reqs),$(addprefix $M/, $(file))))
    $L/lib$(name).tar: $$(L_sources) $(L_reqs)
        tar xvf $L/lib$(name).tar: $(L_sources) $(L_reqs)
endef

$(call my_make_archive, stats,)

all: $L/libstats.tar
    echo foo

I was not able to find any good examples of using defines to generate rules.

Upvotes: 0

Views: 1451

Answers (1)

Beta
Beta

Reputation: 99094

You're making this much too complicated, and your coding is way out ahead of your testing. Try this:

define my_make_archive
 name:=$(strip $1)
 reqs:=$(2)
 L_sources:=$(name).cpp
 L_reqs=$$(addprefix $$L/,$$(reqs))

 $(L)/lib$(name).tar: $$(L_sources) $$(L_reqs)
     tar xvf $$@ $$^

endef

all: $L/libstats.tar
    echo foo

$(eval $(call my_make_archive, stats))

Upvotes: 2

Related Questions