CODEWITHSUNDEEP
vhdl
Nils Pipenbrinck
Nils Pipenbrinck

Reputation: 86353

Unsigned literals in VHDL

How do I use unsigned literals in assignments?

Take a look at this example:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all; 

entity myTest is
    Port ( clk : in STD_LOGIC );
end myTest;

architecture Behavioral of myTest is

  signal testSignal : unsigned (31 downto 0);

begin
    process (clk) is
    begin
        if (rising_edge (clk)) then

           -- this compiles fine:
            testSignal <= testSignal + 1;

            -- this causes an error. Why?
            testSignal <= 1;

        end if;
    end process;
end Behavioral;

The line:

            testSignal <= 1;

results in the following error message on Xilinx ISE:

Line 22. Type of testSignal is incompatible with type of 1.

Can anyone explain why and how to fix this?

Upvotes: 1

Views: 12430

Answers (1)

fru1tbat
fru1tbat

Reputation: 1625

The + operator is overloaded in ieee.numeric_std for unsigned and integer, which is why the first line works; however, assignment is not (and cannot be), and since 1 is an integer literal, it cannot be assigned directly to an unsigned (which is a vector); it must be converted first. The standard method is:

testSignal <= to_unsigned(1, testSignal'length);

to_unsigned() takes 2 arguments: a natural to convert, and the vector length to convert to.

Upvotes: 5

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