CODEWITHSUNDEEP
vhdlcounterclockfpga
Mehmet Salih Cüvelek
Mehmet Salih Cüvelek

Reputation: 201

Using together with rising and falling edges to make a counter?

if rising_edge (clk) then
new_clk <= not new_clk ;
end if;

When using that statement, in fact clock speed is dividing by 2 because one-edge triggering. What if we want to count with a counter which has same speed with clock, what statement is needed? Is there a way to use rising and falling edges together synchronously?

Edit: Because of unclarities..

I am using counter generally to reduce clock speed and make a new clock by using higher indexes of counter bit vector. MSB of the counter vector has the highest frequency blink but its frequency is half of the clock because of rising edge thing. If it is possible to use both of rising and falling edge cases together, MSB's frequency would be equal to clock speed.

And in the code above, a bit is make set and clear at consecutive rising edges. But clock speed dividing again.

Upvotes: 0

Views: 5732

Answers (2)

Morten Zilmer
Morten Zilmer

Reputation: 15924

The question is a bit unclear, but I assume that the intention is to make a counter that increments on both rising and falling edge of a clock.

Usual FPGA and ASIC primitives does include flip-flops that change state on both rising and falling edge, so the assumption also that the target technology only have flip-flops that are sensitive to rising or falling edge.

A counter that effectively increments on every edge can be created if the LSB is made directly from the clock, and the remaining counters bits are generated as a conventional counter. Code can be like below, with final count output on z_o:

-- Resulting counter output combined from ordinary counter and clk_i
z_o <= cnt(cnt'left downto 1) & (not clk_i);

-- Ordinary counter for top of resulting counter
process (clk_i, rst_i) is
begin
  if rising_edge(clk_i) then
    cnt(cnt'left downto 1) <= std_logic_vector(unsigned(cnt(cnt'left downto 1)) + 1);
  end if;
  if rst_i = '1' then
    cnt(cnt'left downto 1) <= (others => '0');
  end if;
end process;

Wave can be seen below:

enter image description here

Note that timing of the resulting counter on z_o will not be as for an ordinary counter where all bits come from flip-flops, so the timing analysis setup may have to be different, depending on how the resulting counter is used.

So an alternative to creating a counter that increments on both edges, it may be worth reconsidering the solution in general and use an ordinary counter instead, since that will simplify timing setup.

Upvotes: 2

MtScor
MtScor

Reputation: 31

1 ) What if we want to count with a counter which has same speed with clock, what statement is needed?

You just need to create a synchronous process like this:

PROCESS(CLK, RESET) 
IF  reset = '1' then
   COUNT <= (OTHERS => '0');
ELSIF rising_edge(clk) then
   COUNT <= COUNT + '1';
END IF;

2) Is there a way to use rising and falling edges together synchronously?

You have to create two processes in this way

PROCESS(CLK,RES)
IF  reset = '1' then
   COUNT_pos <= (OTHERS => '0');
ELSIF rising_edge(clk) then
   COUNT_pos <= COUNT_neg + '1';
END IF;
PROCESS(CLK,RES)
IF  reset = '1' then
   COUNT_neg <= (OTHERS => '0');
ELSIF falling_edge(clk) then
   COUNT_neg <= COUNT_pos + '1';
END IF;

They are just examples you should change this code for your purpose.

Upvotes: 0

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