CODEWITHSUNDEEP
vhdlintel-fpgaquartus
RainingChain
RainingChain

Reputation: 7746

VHDL: How to assign value to an input?

I wrote a "template" for a multiplexer.

My goal is that y=1 when s="01" or s="11".

Now, how am I supposed to link d0 and the value it hold?

(In this example, d0 should hold 0, d1=1, d2=0, d3=1.)

library IEEE;
use IEEE.std_logic_1164.all;

entity mux4v1 is 

 port(
        d0  : in    std_logic;  -- 0
        d1  : in    std_logic;  -- 1
        d2  : in    std_logic;  -- 0
        d3  : in    std_logic;  -- 1
        s   : in    std_logic_vector(1 downto 0); -- my inputs controller via switches
        y   : out   std_logic
    );

end mux4v1;


architecture struct of mux4v1 is

begin
  with s select
  y <= d0 when "00",
       d1 when "01",
       d2 when "10",
       d3 when "11";
end struct;

Upvotes: 1

Views: 14545

Answers (1)

user1818839
user1818839

Reputation:

I THINK what you're asking is how you feed '0' and '1' into the inputs...

The answer is : from outside, in the design that uses the mux.

For simulation, you create a higher level design and instantiate the mux in it. That higher level design could be something like a microprocessor, but here we simply want to test the mux, so we can write a simple testbench for it.

A testbench usually has no inputs or outputs, so it forms the top level of a design, and you run it in a simulator.

entity mux_tb is
end mux_tb;

Inside, it contains the DUT (Device Under Test) and any other components you are testing it with, signals to interconnect them, and processes to generate clocks and other signals, and processes to compare the device outputs against the expected values and report any errors.

architecture simple of mux_tb is

entity mux4v1 is 

signal test_d0 : std_logic := 0;  
signal test_d1 : std_logic := 1;
signal test_d2 : std_logic := 0;
signal test_d3 : std_logic := 0;

signal sel   :   std_logic_vector(1 downto 0); 
signal output :  std_logic;

begin

DUT : entity work.mux4v1
 port map(
        d0  => test_d0,
        d1  => test_d1,
        d2  => test_d2,
        d3  => test_d3
        s   => sel,
        y   => output
    );

Stimulus : process
begin
   sel <= "00";
   wait for 1 us;
   sel <= "01";
   -- and so on
end process;

end simple;

For synthesis, if you simply wanted to implement the MUX in your FPGA, you can synthesise it as-is. Then there is one additional step before you can place and route it to generate a bitfile to program the FPGA.

That step is to allocate device pins to each of the input and output signals.

These pin allocations are made in a constraint file which you write, according to how your FPGA is wired up. For example if there is a switch you wvant to connect to D0 and a LED you want to connect to Y, find out from your board's schematic which FPGA pin the switch is connected to, and write a constraint connecting that pin to input D0. The syntax of this constraint file (and some examples) should be in your FPGA tools documentation.

Upvotes: 2

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