CODEWITHSUNDEEP
buildmakefilegnu-make
j b
j b

Reputation: 5296

How can I pass variables between invocations of GNU Make?

I have a "parent" Makefile, and I am executing other Makefiles from it using make -C.

I am currently passing variables from the parent to its children by appending the variables to the make commands. This makes for quite a cumbersome pattern, for example:

$(MAKE) -C $@ PREFIX="$(PREFIX)" CXXFLAGS="$(CXXFLAGS)" FOO="$(FOO)"

This makes for a lot of repetition, especially if there is a long list of $(MAKE) calls passing similar variables.

Is there a more elegant / optimal way to pass variables to a child invocation of make?

Upvotes: 0

Views: 280

Answers (1)

MadScientist
MadScientist

Reputation: 100846

You can export them through the environment:

export PREFIX CXXFLAGS FOO

However, note that if these variables are actually set in the child makefile then this will not override those settings.

Upvotes: 1

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