CODEWITHSUNDEEP
system-verilog
user2692669
user2692669

Reputation: 461

Assign vs if statement

Is this:

  assign ON = signalA && signalB;
  always_comb begin
    case (blabla)
      case_A: begin
        if (ON) next_state = some_state;
      end
  ...

Equivalent to this:

  always_comb begin
    case (blabla)
      case_A: begin
        if (signalA && signalB) next_state = some_state;
      end
  ...

Do they produce the same amount of hardware? Is one better than the other?

Upvotes: 2

Views: 647

Answers (1)

Ari
Ari

Reputation: 7556

In this case they should produce the same amount of logic.

In general, always_comb is preferred for at least the following reasons:

  • If there is a function on the right hand side and it depends on a global net or variable, then it’s more accurate to use always_comb, because it “is sensitive to changes within the contents of a function”.
  • always_comb will generate warnings about inferred latches.

Equivalently, you could also write:

 always_comb ON = signalA && signalB;
 always_comb begin
    case (blabla)
      case_A: begin
        if (ON) next_state = some_state;
      end
 end

or:

 always_comb begin
    ON = signalA && signalB;
    case (blabla)
      case_A: begin
        if (ON) next_state = some_state;
      end
 end

Note that by assigning signalA && signalB to ON either by continuous assignment or always_comb, you are not creating extra logic. Consider it as an internal signal which exists either way, but you may or may not choose to assign a name to it. One reason to do this is for debugging and viewing the value of signalA && signalB on a waveform display.

Upvotes: 5

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