CODEWITHSUNDEEP
if-statementvhdl
clay-golem
clay-golem

Reputation: 37

If...else error (newbie, VHDL)

I'm having problems with getting this code to work:

if(s="00") then
    f3 <= x and not(y);
elsif(s="11") then 
    f3 <= not(y) xor x;
else 
    f3 <= x or y;
end if;

where:

f3 : out std_logic_vector(2 downto 0);
x, y : in std_logic_vector(2 downto 0);
s : in std_logic_vector(1 downto 0)

Of course I can't really rely on compilation error messages, because they aren't specific about the error. Thanks in advance!

The whole code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity cw1 is
port(
    f0, f2 : out std_logic;
    f3 : out std_logic_vector(2 downto 0);
    a0, a1, a2, a3, a4 : in std_logic;
    x, y : in std_logic_vector(2 downto 0);
    s : in std_logic_vector(1 downto 0)
);
end entity;

architecture A of cw1 is
    signal s1 : std_logic_vector(3 downto 0);
    signal a : std_logic_vector(2 downto 0);
begin
    s1 <= a0 & a1 & a2 & a3;
    a <= a0 & a1 &a2;

with a select
    f2 <= not(a4) when "000",
            a3 when "001"|"010"|"101"|"111",
            a4 or not(a3) when "011"|"100",
            '-' when "110",
            'X' when others;

if s="00" then
    f3 <= x and not(y);
elsif s="11" then 
    f3 <= not(y) xor x;
else 
    f3 <= x or y;
end if;

end A;

Upvotes: 0

Views: 160

Answers (1)

user4227438
user4227438

Reputation:

If you want to use if, you had to put it in a process:

process(s, x, y)
begin
  if(s="00") then
     f3 <= x and not(y);
  elsif(s="11") then 
     f3 <= not(y) xor x;
  else 
     f3 <= x or y;
  end if;
end process;

Upvotes: 2

Related Questions