blueshift
Reputation: 6882
Can I use Vivado block design clock frequencies in my VHDL?
I'm building a design in Vivado and am wondering if I can use the block diagram clock frequencies in my HDL.
I want to take the FREQ_HZ that the block diagram knows about and propagates as part of DRC, and feed it into my custom IP blocks (using a VHDL generic). This is so that I can do things like set up internal counts to generate delays in microseconds, baud rates, etc.
I could do this with a manual Customisation Parameter, but that would need manual maintaining and be prone to error.
Upvotes: 5
Views: 976
Answers (1)
Timmy Brolin
Reputation: 1181
I think TCL might be your only option here. Make a TCL script which runs as a part of your build process, and copy the FREQ_HZ attribute to your generic.
Upvotes: 1
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