CODEWITHSUNDEEP
verilogsystem-verilogmodelsimregister-transfer-level
Prashanth R
Prashanth R

Reputation: 95

The interface port must be passed an actual interface : system verilog

I have a top level file where I have an instance of an interface. This is the code in my toplevel file

LC3_io top_io; // LC3_io is the interface which is defined seperately in my interfaces file.

LC3_test test(top_io); // Passing the interface to my testbench

test is the instance of my LC3_test(Testbench).

Now, after passing this interface to my Testbench . I have a separate testbench file where my first line of code is : 

program automatic LC3_test(LC3_io.TB top_io);

I have written some other code in the testbench.

The problem when I am trying to simulate the testbench is :

**Fatal: (vsim-3695) DUT_Testing.sv(0) : The interface port 'top_io' must be passed an actual interface.
FATAL ERROR while loading design.

I do not understand where the problem could lie. I am compiling all the necessary files using vlog and trying to run/ simulate my testbench using vsim. I have tried removing program and using a module instead for the testbench but the problem persists. Is there anything I am missing here ? Thanks

Upvotes: 0

Views: 6245

Answers (1)

Tudor Timi
Tudor Timi

Reputation: 7573

It seems to me that the types don't match. You're expecting an argument of type LC3_io.TB for your program block, but you're passing in an interface of type LC3_io. Try changing your code to this:

// pass the TB modport from 'top_io'
LC3_test test(top_io.TB);

Upvotes: 2

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