CODEWITHSUNDEEP
moduleverilog
3bdalla
3bdalla

Reputation: 407

Instantiate a module number of times based on a parameter value in Verilog

Assume we have the following arbitrary parameterized module

module module_x #(parameter WIDTH = 1) (in_a, in_b, out);
    input [WIDTH - 1] in_a, in_b;
    output out;

    // Some module instantiation here
endmodule

How do I instantiate another based on the value of WIDTH ? like if it's 5 I instantiate it 5 times on each bit, is it possible to do this in Verilog ?

Upvotes: 2

Views: 1418

Answers (1)

Morgan
Morgan

Reputation: 20514

Generate statements are a common approach to this: Section 27 page 749 of IEEE 1800-1012.

A quick example :

logic [WIDTH-1:0] a;
logic [WIDTH-1:0] b; 

genvar i;
generate
for(i=0; i<WIDTH; i++) begin
  module_name instance_name(
    .a(a[i]), 
    .b(a[i])
  );
end
endgenerate

As @toolic has pointed out instance arrays are also possible, and simpler.

logic clk;
logic [WIDTH-1:0] a_i;
logic [WIDTH-1:0] b_i; 

module_name instance_name[WIDTH-1:0] (
 .clk ( clk ), //Single bit is replicated across instance array
 .a   ( a_i ), //connected wire a_i is wider than port so split across instances
 .b   ( b_i )
);

Upvotes: 4

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