Error after running implementation

Question

I am new to Verilog, therefore I am facing some issues which I am not able to solve on my own. I have made a program that consists of 2 files, synthesis is successful but when I try to generate bitstream, then I face errors which are as follows.

[Opt 31-37] Multi-driver net found in the design: uut/TX_Data_IBUF[0].    
[Opt 31-37] Multi-driver net found in the design: uut/TX_Data_IBUF[10].    
[Opt 31-37] Multi-driver net found in the design: uut/TX_Data_IBUF[11].    
[Opt 31-37] Multi-driver net found in the design: uut/TX_Data_IBUF[12].    
[Opt 31-37] Multi-driver net found in the design: uut/TX_Data_IBUF[13].    
[Opt 31-37] Multi-driver net found in the design: uut/TX_Data_IBUF[14].    
[Opt 31-37] Multi-driver net found in the design: uut/TX_Data_IBUF[15].    
[Opt 31-37] Multi-driver net found in the design: uut/TX_Data_IBUF[1].    
[Opt 31-37] Multi-driver net found in the design: uut/TX_Data_IBUF[2].    
[Opt 31-37] Multi-driver net found in the design: uut/TX_Data_IBUF[3].    
[Opt 31-37] Multi-driver net found in the design: uut/TX_Data_IBUF[4].    
[Opt 31-37] Multi-driver net found in the design: uut/TX_Data_IBUF[5].    
[Opt 31-37] Multi-driver net found in the design: uut/TX_Data_IBUF[6].    
[Opt 31-37] Multi-driver net found in the design: uut/TX_Data_IBUF[7].   
[Opt 31-37] Multi-driver net found in the design: uut/TX_Data_IBUF[8].   
[Opt 31-37] Multi-driver net found in the design: uut/TX_Data_IBUF[9].    
[Opt 31-37] Multi-driver net found in the design: uut/USB_2_RXData_IBUF[0].    
[Opt 31-37] Multi-driver net found in the design: uut/USB_2_RXData_IBUF[10].    
[Opt 31-37] Multi-driver net found in the design: uut/USB_2_RXData_IBUF[11].    
[Opt 31-37] Multi-driver net found in the design: uut/USB_2_RXData_IBUF[12].    
[Opt 31-37] Multi-driver net found in the design: uut/USB_2_RXData_IBUF[13].    
[Opt 31-37] Multi-driver net found in the design: uut/USB_2_RXData_IBUF[14].    
[Opt 31-37] Multi-driver net found in the design: uut/USB_2_RXData_IBUF[15].    
[Opt 31-37] Multi-driver net found in the design: uut/USB_2_RXData_IBUF[1].    
[Opt 31-37] Multi-driver net found in the design: uut/USB_2_RXData_IBUF[2].    
[Opt 31-37] Multi-driver net found in the design: uut/USB_2_RXData_IBUF[3].    
[Opt 31-37] Multi-driver net found in the design: uut/USB_2_RXData_IBUF[4].    
[Opt 31-37] Multi-driver net found in the design: uut/USB_2_RXData_IBUF[5].    
[Opt 31-37] Multi-driver net found in the design: uut/USB_2_RXData_IBUF[6].    
[Opt 31-37] Multi-driver net found in the design: uut/USB_2_RXData_IBUF[7].    
[Opt 31-37] Multi-driver net found in the design: uut/USB_2_RXData_IBUF[8].    
[Opt 31-37] Multi-driver net found in the design: uut/USB_2_RXData_IBUF[9].    
[Opt 31-37] Multi-driver net found in the design: uut/execute_in.

Please see the code below

`timescale 1ns / 1ps

module ber
(
  clk,
  rstn,
  TX_Data [15:0],
  RX_Data [15:0],
  total_error [15:0],
  clear,
  enable
);

//inputs
input clk;
input rstn;
input [15:0] TX_Data;
input [15:0] RX_Data;
input clear;
input enable;
//outputs
output [15:0] total_error;

reg [4:0] i;
reg [15:0] subtotal, next_subtotal;

assign total_error = subtotal;

always @(*) begin : comb
  if (rstn==1'b0)
  begin
    next_subtotal = 0;
  end else
  if (clear==1'b1)
  begin
    next_subtotal = 0;
  end else
  if (enable == 1'b1)
  begin
    for (i = 0; i < 16; i = i + 1)
    begin
      if (TX_Data[i] != RX_Data[i]) 
      begin
        next_subtotal = next_subtotal + 1;
      end
    end
  end
end

always @(posedge clk) begin : dff
  if (rstn==1'b0)
  begin
    subtotal <= 7'b0000000;
  end else
  begin
    subtotal <= next_subtotal;
  end
end

endmodule

Here is the another file which has been instantiated with the above file

// --------------------------------------------------------------------
`timescale 1ns/1ps
module  BitErrorRate
(
    reg_0_in, 
    reg_1_in, 
    reg_2_in, 
    reg_3_in, 
    reg_4_in, 
    reg_5_in,
    reg_6_in, 
    reg_0_out,         
    reg_1_out,         
    reg_2_out,         
    reg_3_out,         
    reg_4_out,         
    reg_5_out,         
    reg_6_out,
//-----------------
    clk,
    resetn,
    TX_Data [15:0],
    TX_Valid,
    TX_Ready,
    TX_Last,
    USB_2_RXData [15:0],
    USB_2_RXActive,
    USB_2_RXValid
);
//-------------------
input [31:0] reg_0_in; //
input [31:0] reg_1_in; //
input [31:0] reg_2_in; //
input [31:0] reg_3_in; //
input [31:0] reg_4_in; //
input [31:0] reg_5_in; //
input [31:0] reg_6_in; //

output [31:0] reg_0_out;
output [31:0] reg_1_out;
output [31:0] reg_2_out;
output [31:0] reg_3_out;
output [31:0] reg_4_out;
output [31:0] reg_5_out;     
output [31:0] reg_6_out;     

//-----------------------------------USB20 BER interface
input     resetn, clk;

input [15:0] TX_Data;
input TX_Last;          
input TX_Valid;
output TX_Ready;    

input [15:0] USB_2_RXData;
input USB_2_RXActive;
input USB_2_RXValid;
//-----------------------------------
reg [31:0] reg_0_out;
reg [31:0] reg_1_out;
reg [31:0] reg_2_out;
reg [31:0] reg_3_out;
reg [31:0] reg_4_out;
reg [31:0] reg_5_out;
reg [31:0] reg_6_out;
reg [6:0] sel;


reg        start; //converted from change_enb
reg        execute;
reg        execute_in,execute_reg,execute_ack;
wire       execute_enb;
reg        store_config_in, store_config;
wire       busy, busy_d2;

parameter IDLE_STATE=3'd0,
          COUNT_STATE=3'd1; // running

reg [15:0] T_Data; 
reg [15:0] R_Data; 
reg T_Ready;


assign TX_Data = T_Data;
assign USB_2_RXData = R_Data;
assign TX_Ready = T_Ready;

//INSTANTIATION OF BER (unit under test)
ber uut
(
  .clk(clk),
  .rstn(resetn),
  .TX_Data(TX_Data),
  .RX_Data(USB_2_RXData),
  .total_error(total_error),
  .clear(clear_err_cnt),
  .enable(execute_in)
);

//------------------------------------------
always @(posedge clk)
    execute_reg<=execute;

always @(posedge clk)
        execute_ack<=execute_reg;


assign execute_enb=execute_reg&&(!execute); //1 to 0 ,negative edge
assign clear_err_cnt = reg_0_in[1];
assign TX_Ready = reg_0_in[2];
//------------------------------------------


//------------------------------------------        
always @( posedge clk or negedge resetn)
begin
    if( resetn == 1'b0 )
    begin
        {execute, execute_in}           <= 2'd0;
        {store_config, store_config_in} <= 2'd0;

    end
    else
    begin
      execute_in      <= reg_0_in[0]; // sampling only

      if (execute_ack) 
        execute     <= 1'b0;
      else
        execute         <=execute_in;  

      {store_config, store_config_in} <= {store_config_in, reg_0_in[1]};
    end
end

//------------------------------------------
always @( posedge clk or negedge resetn)
begin
        if( resetn == 1'b0 )
        begin
          reg_0_out   <= 32'h0;
          reg_1_out   <= 32'h0;
          reg_2_out   <= 32'h0;
          reg_3_out   <= 32'h0;
          reg_4_out   <= 32'h0;
          reg_5_out   <= 32'h0;
          reg_6_out   <= 32'h0;
        end
        else
        begin
          reg_0_out[0]   <= busy || busy_d2 || execute || execute_ack ;
          reg_0_out[1]   <= store_config;
          reg_0_out[2]   <= reg_0_in[2];
          reg_0_out[3]   <= TX_Valid;
          reg_0_out[4]   <= TX_Last;
          reg_0_out[31:5] <= reg_0_in[31:5];        
          reg_1_out <= reg_1_in;
          reg_2_out <= reg_2_in;
          reg_3_out <= total_error;
          reg_4_out <= reg_4_in;         
          reg_5_out <= reg_5_in;
          reg_6_out <= TX_Data[15:0];
        end
end
//------------------------------------------
always @ (posedge clk)  //making a function for start using mux
begin
  if (execute_in == 1'b1) //before was 1'b0 that will make the value to be 0
  begin
    T_Data <= reg_4_in[15:0]; //loading the contents of register 4 in data_1
    R_Data <= reg_5_in[15:0]; //loading the contents of register 5 in data_2
  end
  else
  begin
    T_Data <= 16'b0; //if start is not equal to 1, then the data is 0
    R_Data <= 16'b0; //if start is not equal to 1, then the data is 0
  end
end
//------------------------------------------
//making state machine here
//using non blocking assignment
always @ (posedge clk or negedge resetn)
begin
    if (resetn == 1'b0) //idle state
    begin
        sel <= 7'b0000000; //state 0
    end
    else if (TX_Valid == 7'b0000001)
    begin
        sel <= 7'b0000001; //state 1
    end
    else if (sel == 7'b0000001)
    begin
        sel <= 7'b0000010; //state 2
    end
    else if (USB_2_RXActive == 7'b0000001)
    begin
        sel <= 7'b0000011; //state 3
    end
    else if (TX_Valid == 7'b0000001 && USB_2_RXValid == 7'b0000001)
    begin
        sel <= 7'b0000100; //state 4
    end
    else if (sel == 7'b0000100)
    begin
        sel <= 7'b0000101; //state 5
    end
    else if (TX_Valid == 7'b0000000 && USB_2_RXValid == 7'b0000000)
    begin
        sel <= 7'b0000100; //goes back to state 4
    end
end
//------------------------------------------
//making outputs for state machine
//using blocking assignment here
always @ (*)
begin
    case (sel)
        7'b0000000 :
            execute_in = 1'b0;  //state 0
        7'b0000001 :
            T_Ready    = 1'b1;  //state 1
        7'b0000010 :
            T_Ready    = 1'b0;  //state 2
        7'b0000011 :
            execute_in = 1'b1;  //state 3
        7'b0000100 :
            T_Ready    = 1'b1;  //state 4
        7'b0000101 :
            T_Ready    = 1'b0;  //state 5
    endcase
end
//------------------------------------------
endmodule

I am using Vivado 2014.3 software. Kindly help me with this.

Answer 1

You set values to input signals ! This is not allowed, you shall set value to output signals.

for example in module "BitErrorRate", "USB_2_RXData" is define as input.

input [15:0] USB_2_RXData;

but you set a value to this input :

assign USB_2_RXData = R_Data;

to solve the problem, define USB_2_RXData as output.

output [15:0] USB_2_RXData;

Answer 2

A CRITICAL WARNING multi-driven net message and Multi-driver net found in the design error informs you that in your code you try to drive a net in (at least) 2 different places. That's not allowed.

For example, you drive execute_in for the first time here:

always @( posedge clk or negedge resetn)
  begin
    if( resetn == 1'b0 )
      begin
       {execute, execute_in}           <= 2'd0;
       ...
      end
...

But later you want to assign a value to this net in different always block:

always @ (*)
begin
  case (sel)
    7'b0000000 :
        execute_in = 1'b0;
...

You need to rewrite your logic that you'll drive each net only in one always block.

The second thing are issues with port declaration styles (as mentioned by @Morgan).

Answer 3

I am not sure this is the problem but you have mixed port declaration styles.

module ber
(
  clk,
  rstn,
  TX_Data [15:0],
...
);

//inputs
input clk;
input rstn;
input [15:0] TX_Data;
...

If your using this style, then the list should not include dimension, it should just be the name. The modern style reduces the code required and removes the issue:

module ber
(
  input             clk,
  input             rstn,
  input      [15:0] TX_Data,
  //...
  output reg [15:0] total_error //Direction type width and name
);