CODEWITHSUNDEEP
system-verilog
awill
awill

Reputation: 135

how to runtimely show call stack in system verilog?

currently i use this way, when run time error happens, vcs will print call stack. It is very low effecient. Is there a better way?

function void anyFunctionIWouldLikeToSeeCallStack();
uvm_object a;
// a == null
a.print();
endfunction;

Upvotes: 2

Views: 5184

Answers (5)

shaik azar AzarmadR
shaik azar AzarmadR

Reputation: 25

In VCS, you can use $stack() or $psstack() (returns a string). The depth can be configured using -frames <num>.

For more info, [VCS][Documentation][VCS® MX/VCS MXi™ User Guide]Verilog Compiler Directives and System Tasks’

PS: this is the extension of this answer by @user7952785

Upvotes: 0

sean
sean

Reputation: 71

in RivieraPro, the command is $callstack(). There are a few options you can pass to configure the output.

See the documentation: R-PRO: User's Guide | SystemVerilog Simulation | SystemVerilog Non-standard Extensions | $callstack system function

Upvotes: 0

user7952785
user7952785

Reputation: 36

in VCS, it's $stack()

but it's only about 8 levels of the stack, and I don't think that's configurable

Upvotes: 1

krupan
krupan

Reputation: 3959

Cadence incisive (ncsim) has a $stacktrace system task that you can call. I wouldn't be surprised if the other vendors have a similar thing.

Upvotes: 2

Tudor Timi
Tudor Timi

Reputation: 7573

This is the kind of thing a simulator usually provides while setting breakpoints. After reaching a certain breakpoint your simulation will stop and you'll be able to run a simulator specific command to print the call stack or you'll have the call stack shown in some GUI window.

You'll have to look up in the VCS documentation how this is done exactly.

Upvotes: 0

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