CODEWITHSUNDEEP
interruptz80
Hennes
Hennes

Reputation: 1370

Z80 Multibyte Commands in IM0

I'm trying just for the fun to design a more complex Z80 CP/M system with a lot of peripheral devices. When reading the documentation I stumbled over an (undocumented?) behaviour of the Z80 CPU, when accepting an interrupt in IM0.

When an interrupt occurs, the Z80 activates M1 and IORQ to signal the external device: "Hey, give me an opcode". All is well if the opcode is rst 00 or something like this. Now the documentation tells, ANY opcode of any command can be given to the cpu, for instance a CALL.

But now comes the undocumented part: "The first byte of a multi-byte instruction is read during the interrupt acknowledge cycle. Subsequent bytes are read in by a normal memory read sequence."

A "normal memory read sequence". How can I determine, if the CPU wants to get a byte from memory or instead the next byte from the device?

EDIT: I think, I found a (good?) solution: I can dectect the start of the interrupt acknowlegde cycle by analyzing IORQ and M1. Also I can detect the next "normal" opcode fetch by analyzing MREQ and M1. This way I can install a flip-flop triggered by these two ANDed signals, i.e. the flip-flop is 1 as long as the CPU reads data from the io-device. This 1 I can use to inhibit the bus drivers to and from the memory.

My intentions? I'm designing an interrupt controller with 8 prioritized inputs in a CPLD. It's registers hold a 16 bit address for each interrupt pin. Just for the fun :-)

Upvotes: 4

Views: 1695

Answers (2)

jmn
jmn

Reputation: 1364

The interrupt behavior is reasonably documented in the Z80 manual: Interupt modes, IM2 allows you to supply an 8-bit address to a 16-bit pointer. At least halfway to the desired 16-bit direct address.

How to set the interrupt modes

My understanding is that the M1 + IORQ combination is used since there was no pin left for a dedicated interrupt response. A fun detail is also that the Zilog I/O chips like PIO, SIO, CTC reads the RETI instruction (as the CPU fetches it) to learn that the CPU is ready to accept another interrupt.

Upvotes: 0

Tommy
Tommy

Reputation: 100622

My understanding is that the peripheral device is required:

  • to know how many bytes it needs to feed;
  • to respond to normal read cycles following the IORQ cycle; and
  • to arrange that whatever would normally respond to memory read cycles does not do so for the duration.

Also the behaviour was documented by Zilog in an application note, from which your quote originates (presumably uncredited).

In practice I guess 99.99% of IM0 users just use an RST and 99.99% of the rest use a known-size instruction like CALL xxxx.

(also I'm aware of a few micros that effectively guaranteed not to put anything onto the bus during an interrupt cycle, thereby turning IM0 into a synonym of IM1 owing to open collector output).

Upvotes: 6

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