CODEWITHSUNDEEP
vhdl
felipeek
felipeek

Reputation: 1213

VHDL generating control signals as flip-flops

I created a finite state machine with four states using VHDL, but I'm having a problem to understand what is happening with the control signals that the FSM generates. I was expecting that these signals were generated dynamically without the need of storing it in flip-flops, but this is not happening - the synthesis is creating flip-flops for all of them.

To illustrate my problem, I'll put part of my code here:

For example, this is a register that I use:

-- register
signal register : STD_LOGIC_VECTOR (2 downto 0);
signal in_register : STD_LOGIC_VECTOR (2 downto 0);
signal c_register : STD_LOGIC;

-- 

-- register logic
process (clock)
begin
    if (clock = '1' and clock'event) then
        if (reset = '1') then
            register <= "000";
        elsif (c_register = '1') then
            register <= in_register;
        else
            register <= register;
        end if;
    end if;
end process;

My FSM must generate the c_register signal, and it is similar to this:

-- FSM
process (clock)
begin
    if (clock = '1' and clock'event) then
         if (reset = '1') then
              c_register <= '0';
              state <= A;
              ...
         else
             case state is
                 when A =>
                     c_register <= '0';
                     state <= B;
                     ...
                 when B =>
                     c_register <= '0';
                     state <= C;
                     ...
                 when C =>
                     if (X) then
                         c_register <= '0';
                     else
                         c_register <= '1';
                     end if;
                     state <= D;
                 when D =>
                     c_register <= '0';
                     state <= A;
             end case;
         end if;
    end if;
end process;

My FSM is not exactly the same that I showed above, but as you can see I give a value to c_register in every state, just to be sure that the VHDL compiler will not think that I want a flip-flop to store an older value.

When I compile it, the c_register signal becomes a flip-flop!

I'm a bit confused. Appreciate any help! Thanks!

Upvotes: 1

Views: 1112

Answers (1)

user1155120
user1155120

Reputation:

You could convert c_register to a Mealy Finite State Machine output by moving it's assignment outside the clocked process.

Something along the line of:

c_register <= '1' when state = A and X = '0' else
              '0';

And about now someone viewing your incomplete VHDL example might wonder at the 'register' in the signal name. Does c_register control a register?

Note there are several other forms of assignment possible besides the above shown concurrent conditional signal assignment that could be used. For instance there's an equivalent process statement along the lines of:

process (state,X)
begin
    if state = A and X = '0' then
        c_register <= '1';
    else 
        c_register <= '0';
    end if;
end process;

If A represented a one hot value as a state (where the states are held exclusive of each other in separate flip flops) the concurrent assignment could be expressed even more simply:

 c_register <= A and not X;

The operative idea for a non-registered Mealy State Machine output is that as Paebbels points out the assignment occurs outside a sequential logic inferring statement (in your example a clock process).

Upvotes: 1

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