4 bit Bi-Directional counter in verilog

Question

My assignment asks that 4 bit Bi-Directional counter will be designed which counts increasingly from 0 to 12 by twos, after reaching 12, decreasingly from 12 to 0 by three at a time (0 2 4 6 8 10 12 9 6 3 0 2 4...). until the program terminates by user with "stop" command, this loop should continue this project will be designed by flip flops and D flip flops must be used

Here is the my verilog code. When i create textbench file i gives error:

module CounterTopLevel(
input clk,
 input rst,
input stop,
output [3:0] counter_out
);

//-----------Input Ports---------------
//input clk, stop;

//-----------Output Ports---------------
//output reg [3:0] counter_out;
//initial counter_out = 4'b0000;

//------------Internal Variables--------

 wire rst;
 wire stop;
 wire clk;
 wire [3:0] counter_out;
 wire q3;
 wire q2;
 wire q1;
 wire q0;
 wire d3;
 wire d2;
 wire d1;
 wire d0;

//D3=Q3Q0' + Q2Q1Q0 
//D2= Q2Q1' + Q2Q0' + Q2'Q1Q0 
//D1= Q3'Q1'Q0 + Q1Q0'
//D0= Q0' 

//Z3=Q2
//Z2= Q3Q0' + Q2'Q1 + Q1Q0'
//Z1= Q3 + Q2'Q0
//Z0= Q3Q0 + Q2Q1Q0
assign d3 =  (q3 & ~q0) | (q2 & q1 & q0);
assign d2 =  (q2 & ~q1) | (q2 & ~q0) | (~q2 & q1 & q0);
assign d1 =  (~q3 & ~q1 & q0) | (q1 & ~q0);
assign d0 =  ~q0;
assign counter_out[3] =  q2;
assign counter_out[2] =  (q3 & ~q0) | (~q2 & q1) | (q1 & ~q0);
assign counter_out[1] =  q3 | (~q2 & q0) | (~q1 & q0);
assign counter_out[0] = (q3 & q0) | (q2 & q1 & q0);

DFF DFF0 (
    .clk(clk),
     .rst(rst),
    .d(d0),
     .stop(stop),
    .q(q0)
    );

DFF DFF1 (
    .clk(clk),
    .rst(rst),   
    .d(d1), 
     .stop(stop),
    .q(q1)
    );

DFF DFF2 (
    .clk(clk),
     .rst(rst),
    .d(d2),
     .stop(stop),    
    .q(q2)
    );

DFF DFF3 (
    .clk(clk),
    .rst(rst),   
    .d(d3),
    .stop(stop),     
    .q(q3)
    );
endmodule

module DFF(
input clk,
 input rst,
input d,
 input stop,
output reg q
);

   always @(posedge clk) begin
    if (rst == 1'b1) begin
        q <= 1'b0;
    end
    else begin
        if (stop == 1'b1) begin
            q <= q;
        end
        else begin
            q <= d;
        end
    end
   end
endmodule

Here is the textbench:

module test2;

// Inputs
reg clk;
reg rst;
reg stop;

// Outputs
wire [3:0] counter_out;

// Instantiate the Unit Under Test (UUT)
CounterTopLevel uut (
    .clk(clk), 
    .rst(rst), 
    .stop(stop), 
    .counter_out(counter_out)
);

initial begin
    // Initialize Inputs
    clk = 0;
    rst = 0;
    stop = 0;
    // Wait 100 ns for global reset to finish
    #100;
    rst=1;
    #100;
    clk=1; ===> line 28
    #20;
    rst=0;
    clk=0;
    #20; ===>line 32
    clk=1;
    #20;
    clk=0;
    #20;
    clk=1;
    #20;
    clk=0;
    #20;
    clk=1;
    #20;
    clk=0;
    #20;
    clk=1;
    #20;
    clk=0;
    stop=1;
    #20;
    clk=1;
    #20;
    clk=0;
    #20;
    clk=1;
    stop=0;
    #20;
    clk=0;
    #20;
    clk=1;
    #20;
    clk=0;
    #20;
    clk=1;
    #20;
    clk=0;
    #20;
    clk=1;
    #20;
    clk=0;
    #20;
    clk=1;
    #20;
    clk=0;
    #20;
    clk=1;
    #20;
    clk=0;
    #20;
    clk=1;
    #20;
    clk=0;
    #20;
    clk=1;
    #20;
    clk=0;
    #20;

    // Add stimulus here

end

endmodule

It gives this error:

ERROR:HDLCompiler:806 - "C:/Users/Ahmed Yasin/Desktop/exps/cift_yonlu_sayaci/test2.v" Line 28: Syntax error near ";".
ERROR:HDLCompiler:806 - "C:/Users/Ahmed Yasin/Desktop/exps/cift_yonlu_sayaci/test2.v" Line 32: Syntax error near "(".
ERROR:ProjectMgmt - 2 error(s) found while parsing design hierarchy.

how can i fix?

Answer 1

I have tried it on EDA Playground. It worked fine with some minor changes.

CounterTopLevel I had to remove the redeclaration of rst, stop, clk and counter_out.

For your testbench clock you might want to consider some thing along the lines of:

initial begin
  clk =0;
  forever begin
    #20 clk = ~clk;
  end
end

for test program you can then do:

initial begin
  rst =0;
  stop=0;
  @(posedge clk);
  @(posedge clk);
  rst=1;
  repeat(10) 
    @(posedge clk);  //Wait ten clock edges until setting stop
  stop=1;
end