CODEWITHSUNDEEP
randomconstraintssystem-verilog
Réz
Réz

Reputation: 1

SystemVerilog random data generated only for valid signal

I am new to SV and would like to get some opinions about randomization. I have two signals.

rand bit [20:0] data;
rand bit data_valid;

I want to generate random data only when data_valid signal goes high. When valid signal is low, data should contain the previous signal. I have tried the following on 

constraint valid_data {data -> data_valid ==1'b1; }

It generates random data when valid signal is high but then data becomes 0 when valid signal goes low. Is there any other way to do that? What I want is data signal should not change when valid becomes low. It should keep the current value of valid signal goes low.

Another issue is the randomization of data_valid signal. This is a 1 bit signal and I want to make this signal high randomly for 1 clock cycle only. At the moment it can remain high for any clock cycles which I don't want.

Upvotes: 0

Views: 1219

Answers (2)

dave_59
dave_59

Reputation: 42623

You need to build a state machine by saving a copy of the previously generated values

class tx;
  rand bit [20:0] data;
  rand bit data_valid;
  bit [20:0] prev_data;
  bit prev_data_valid;
  function void post_randomize;
    prev_data = data;
    prev_data_valid = data_valid;
  endfunction
  constraint one_cycle { prev_data_valid -> data_valid == 0;}
  constraint latch_data { !prev_data_valid -> data == prev_data;}
endclass

This works assuming you call randomize() once per clock cycle.

Upvotes: 1

Réz
Réz

Reputation: 1

OK, I was able to solve my first problem. But still can not figure out how to generate random valid signal which will stay high one clock cycle only. Any tips would be appreciated.

Upvotes: 0

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