CODEWITHSUNDEEP
unit-testingparameterizedspecman
Lior Bekerman
Lior Bekerman

Reputation: 3

Specman Parametrized Unit

I Need to verify a paramterized module in verilog, for example:

module A #(PAR1, PAR2, PAR3) (/*input, outputs*/);

This module is instantiated several times with different values of parameters.

I need to generate a SPECMAN Unit which can get PARAMETERs as constant for variable/port declaration. Those parameters are also used for logic calculation.

I could not find a way to pass PARAMETERs to a specman unit as it can be done in verilog.

Is it possible?

If not - are there alternative solution?

Upvotes: 0

Views: 525

Answers (3)

Thorsten
Thorsten

Reputation: 700

You can access Verilog parameters via simple_ports from e-code, just bind them like normal signals. But it wouldn't help in this case because the values can't be used in other port declarations. I suggest to use the solutions offered here or make the ports wide enough to capture all requirements (MSBs would be filled with 1'b0 by Specman per default).

Upvotes: 0

Tudor Timi
Tudor Timi

Reputation: 7573

There's no way to pass parameters to units in e. What you can do in your case, however, is used a template:

template unit some_unit of (<len'type>) {
  some_sig : in simple_port of <len'type> is instance;
    keep soft some_sig.hdl_path() == "some_sig";
};

The code above will define a template for a unit that contains a port, whose length is specified when declaring the unit instance. Here's how you can instantiate two units with different lengths:

extend sys {
  unit1 : some_unit of (uint(bits : 2)) is instance;
  unit2 : some_unit of (uint(bits : 4)) is instance;
};

You can find a working example on EDAPlayground.

Upvotes: 3

Yuri Tsoglin
Yuri Tsoglin

Reputation: 963

Yes, in e you can define template struct or units. However, note that the parameters would be types rather than values. For example, you can have a declaration like this:

template unit my_unit of (<first'type>, <second'type>) like base_unit {
    ......
};

and then you can instantiate it like this:

extend sys {
    foo: my_unit of (int(bits: 16), uint) is instance;
};

Upvotes: 1

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