CODEWITHSUNDEEP
makefilegnu-make
Abhijatya Singh
Abhijatya Singh

Reputation: 642

Makefile include header file from other directory

I have a drectiry subdir-test with subdirectory obj bin src include in that. I have 3 makefile in that one in src one in obj and one in sub-test. I want to use recursive make in that but I have a error. Directory Structure is :

   subdir-test

      - Makefile1
      - src
           - all.c files and Makefile2
      - obj
           - all.o files and Makefile3
      - include
           - functions.h
      - bin

And Here are the make files: Makefile1:

   SUBDIRS = src obj

   subdirs : 
         for dir in $(SUBDIRS);\
         do \
         $(MAKE) -C $$dir ;\
         done

  .PHONY : clean

  clean : 
         rm -rf bin/* obj/*

Makefile2:

   inc = -I ../include/ 

   all : main.o factorial.o 

   main.o : main.cpp functions.h 
       cc -c $< -I $(inc) -o ../obj/$@ -lstdc++

  factorial.o : factorial.cpp functions.h
      cc -c $< -I $(inc) -o ../obj/$@ -lstdc++

Makefile3:

 run : main.o factorial.o
      cc $^ -o ../bin/$@

While calling make -f Makefile1 from sub-test directory I get the following error : 

  for dir in src obj;\
    do \
    make -C $dir ;\
   done
make[1]: Entering directory `/home/betatest/Public/subdir-test/src'
make[1]: *** No rule to make target `functions.h', needed by `main.o'.  Stop.
make[1]: Leaving directory `/home/betatest/Public/subdir-test/src'
make[1]: Entering directory `/home/betatest/Public/subdir-test/obj'
make[1]: *** No rule to make target `main.o', needed by `run'.  Stop.
make[1]: Leaving directory `/home/betatest/Public/subdir-test/obj'
make: *** [subdirs] Error 2

And I have an other problem as I want to write for loop as follows:

  for dir in $(SUBDIRS)
  do
    $(MAKE) -C $$dir
  done

There I am getting error in for loop also. Where am I getting wrong.

Upvotes: 0

Views: 4381

Answers (1)

cacsar
cacsar

Reputation: 2138

With your makefiles written like this I believe using relative paths to the dependencies will solve your problem. You can leave Makefile1 the way it is since you are processing the directories in the correct order.

Makefile2 would become:

   inc = -I ../include/ 

   all : main.o factorial.o 

   main.o : main.cpp ../include/functions.h 
       cc -c $< -I $(inc) -o ../obj/$@ -lstdc++

   factorial.o : factorial.cpp ../include/functions.h
      cc -c $< -I $(inc) -o ../obj/$@ -lstdc++

And makefile3 can probably stay the same since main.o and factorial.o don't exist in obj/ only because of the errors in makefile2.

Note that currently main.o and factorial.o will always be compiled (and should potentially go with .PHONY) as the target is really ../obj/main.o, similarly for run -> ../bin/run. I don't think you gain much by using three different makefiles in this case, but that's up to you.

Upvotes: 1

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