CODEWITHSUNDEEP
assemblymemoryembeddedprocessorxtensa
ARF
ARF

Reputation: 7694

Xtensa instruction: L32R - which addres is loaded?

I am trying to read some xtensa assembly code and am stumped by the L32R instruction:

E.g. given the following line:

0000 2f04 <my_func>:
     2f0c:  ffef21          l32r    a2, 2ec8

Which address does this load?

Upvotes: 2

Views: 3159

Answers (2)

egbit
egbit

Reputation: 69

The L32R instruction loads a 32-bit value from the indicated address. So "l32r a2, 2ec8" loads the 32-bit value located at address 0x2ec8 into register a2. You'll have to look at that location in your disassembly.

Upvotes: 0

ARF
ARF

Reputation: 7694

The Xtensa Instruction Set Architecture Reference Manual manual states on page 382 that for l32r the address is calculated as follows:

L32R forms a virtual address by adding the 16-bit one-extended constant value encoded
in the instruction word shifted left by two to the address of the L32R plus three with the
two least significant bits cleared. Therefore, the offset can always specify 32-bit aligned
addresses from -262141 to -4 bytes from the address of the L32R instruction. 32 bits
(four bytes) are read from the physical address.

So in continuing above example; manipulation of the constant:

     ffef    16-bit constant
ffff ffef    16-bit constant one-extended
ffff ffbc    shifted left by two

Manipulation of the PC:

0000 2f0c    program counter
0000 2f0f    pc +3
0000 0f0c    masked bits 0 and 1

calculation of virtual address:

  ffff ffbc
+ 0000 2f0c
===========
1 0000 2ec8

So discarding everything beyond 16-bit: 2ec8

Upvotes: 5

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