CODEWITHSUNDEEP
vhdlmultiplicationhdlfixed-point
Raj
Raj

Reputation: 195

Multiplication with Fixed point representation in VHDL

For the fixed point arithmatic I represented 0.166 with 0000 0010101010100110 and multiply it with same. for this I wrote the code in VHDL as below. Output is assigned in y which is signed 41bit. For signed Multiplication A(a1,b1)*A(a2,b2)=A(a1+a2+1,b1+b2). However during the simulation its give an error 

      Target Size 41 and source size 40 for array dimension 0 does not match.

code: 

 entity file1 is
    Port ( y : out signed(40 downto 0));
 end file1;

 architecture Behavioral of file1 is

 signal a : signed(19 downto 0) := "00000010101010100110";
 signal b : signed(19 downto 0) := "00000010101010100110";

 begin
    y<= (a*b);    ----error
 end Behavioral;

Upvotes: 1

Views: 7268

Answers (1)

dk14
dk14

Reputation: 22374

The result of multiplying 19+1 bits to 19+1 bits is 39+1 bits, while your port is 40+1 bit long. For example let's multiply maximum possible values for 19-bits: 0x7FFFF * 0x7FFFF = 0x3FFFF00001 - so it's 39 bits (19 + 19 + carry) for unsigned result and +1 bit for sign.

So you should either "normalize" result by extending it to 1 more bit, which should be equal to the sign of result (bit#40 = bit#39) or just choose 40-bit port as output:

Port ( y : out signed(39 downto 0))

If you really need redundant 41st bit:

begin
   y(39 downto 0) <= (a*b)
   y(40) <= y(39)
end Behavioral;

Or just use resize function for signeds: How to convert 8 bits to 16 bits in VHDL?

Upvotes: 2

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