CODEWITHSUNDEEP
arraysveriloghdl
Márcio Moura
Márcio Moura

Reputation: 11

VerilogHDL - Error connecting Array with non-Array expressions

I am struggling with my code, which is a Carry-Save Multiplier. 

module csm (A,B,So,Co);

parameter n = 8, m = 16;
input [7 : 0] A,B;
output [m-1 : 0] So;
output Co; // carry out

wire [7:0] CARRY [7:0];
reg [8:0] SUM [8:0];

assign So = {SUM[7][7],SUM[6][7],SUM[5][7],SUM[4][7],SUM[3][7], SUM[2][7],SUM[1][7],SUM[0][7],SUM[0][6],SUM[0][5],SUM[0][4],SUM[0][3],SUM[0][2],SUM[0][1],SUM[0][0]};

genvar i, j;
// Assign Carry out to the last carry related w/ overflow
assign Co = CARRY[7][7];
// Assign A[n] to SUM
//assign SUM[i][j] = {A[i],B[j]};
always@(*)
begin
 SUM[0][0] <= A[0];
 SUM[1][0] <= A[1];
 SUM[2][0] <= A[2];
 SUM[3][0] <= A[3];
 SUM[4][0] <= A[4];
 SUM[5][0] <= A[5];
 SUM[6][0] <= A[6];
 SUM[7][0] <= A[7];
 SUM[7][1] <= A[7];
 SUM[7][2] <= A[7];
 SUM[7][3] <= A[7];
 SUM[7][4] <= A[7];
 SUM[7][5] <= A[7];
 SUM[7][6] <= A[7];
 SUM[7][7] <= A[7];
end
//Assign B[n] to SUM
/*
assign SUM[i][0] = B[0];
assign SUM[i][1] = B[1];
assign SUM[i][2] = B[2];
assign SUM[i][3] = B[3];
assign SUM[i][4] = B[4];
assign SUM[i][5] = B[5];
assign SUM[i][6] = B[6];
assign SUM[i][7] = B[7];
*/
/*
generate
    for(i=0; i <= 7; i = i + 1) // first row (J=0)
    begin : first row
        full_adder fa_1(.A_i(SUM[i][0]),.B_i(B[0]),.C_i(1'b0),.S_o(SUM[i][0]),.C_o(CARRY[i][0]));
    end
endgenerate
*/
generate 

    for(i=0; i <= 7; i = i + 1) // first row (J=0)
    begin : first_row
        full_adder fa_1(.A_i(SUM[i][0]),.B_i(B[0]),.C_i(1'b0),.S_o(SUM[i][0]),.C_o(CARRY[i][0]));
    end

    for(j = 1; j <= 7; j = j + 1)
    begin : column
        for(i=0; i <= 7; i = i + 1) // other rows[]
        begin : row
            full_adder fa(.A_i(SUM[i+1][j-1]),.B_i(B[j]),.C_i(CARRY[i][j-1]),.S_o(SUM[i][j]),.C_o(CARRY[i][j]));
        end
    end
endgenerate

endmodule 


// Full Adder module 

module full_adder(A_i, B_i, C_i, C_o, S_o);

input  A_i, B_i, C_i;
output C_o, S_o;

wire  A_i, B_i, C_i;
wire C_o;
reg S_o;

//assign 
always@(*)
begin
S_o = (A_i ^ B_i ^ C_i);
end 
assign C_o = ((A_i & B_i) | (B_i & C_i) | (A_i & C_i)); 

endmodule

I'm getting this error in Quartus: "Error (10663): Verilog HDL Port Connection error at csm.v(59): output or inout port "S_o" must be connected to a structural net expression"

I am just not seeing the error. If you guys have a tip to me, I'll appreciate a lot (I have to finish this code ASAP :( ).

Thank you all.

Upvotes: 1

Views: 1532

Answers (2)

Greg
Greg

Reputation: 19112

S_o is an output assigning SUM, which is a reg, this is illegal. Even if it were legal, there are also multiple drivers on all SUM[i][0] and you have it feeding back on itself.

full_adder fa_1(.A_i(SUM[i][0]),.B_i(B[0]),.C_i(1'b0),.S_o(SUM[i][0]),.C_o(CARRY[i][0]));

Change reg [8:0] SUM [8:0]; to wire [8:0] SUM [8:0]; and delete the always block (or convert to assign statements). Then fix you generate loops. You may want to consider drawing out a block diagram to visualize the connections of the full-adders.

Upvotes: 2

godel9
godel9

Reputation: 7390

You cannot connect an output port to a constant or a variable (e.g. a reg):

http://quartushelp.altera.com/13.0/mergedProjects/msgs/msgs/evrfx_veri_not_a_structural_net_expression.htm

Upvotes: 1

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