Reputation: 75
I have a PCIe generated core / endpoint with the xilinx core generator tool for a spartan6 fpga on a development board which I have modified a bit to enable MSI and send these every couple of seconds.
Also, I did a simple C kernel module on my linux desktop in which I plugged in the development board. This registers device, allocates memory, enables bus mastership for device and handles the interrupts etc.
What I want to do now is some DMA transfer from the board to the PC, and then will send an interrupt when finished, so that the cpu can go and read it. I'm not a Verilog expert, and the code I have doesn't seem to be capable of any DMA functions.
I couldn't find any relevant information online, so this is my last hope.
Upvotes: 4
Views: 1457
Reputation: 16221
Original text from comment above:
Have you implemented a transaction layer above the generated PCIe core? Why don't you use a free PCIe core if your HDL skills are not so high? PCIe is a very big thing....
Yes, the Xilinx IPCore generator adds a very simple PIO interface ontop of the link layer to handle simple PIO transactioons. Note: PIO transaction are outdated and not allowed for new devices.
Currently I know two rather good IPCores:
/dev/xillybus_read
/dev/xillybus_write
devicesAll these cores require the Xilinx Core Generator to generate a PCIe core for your device/board. The core itself provides transaction handling, ...
Upvotes: 3