CODEWITHSUNDEEP
system-verilogassertionssystem-verilog-assertions
Cody
Cody

Reputation: 13

Does $stable in SystemVerilog Operate on Buses?

I would like to verify that a bus is stable in an assertion. For example, I would expect the following assertion to flag an error if data changes in the clock after the re falling edge.

wire clk, rst_n, re;
wire [15:0] data;

a_chk_stable_data:
  assert property (@(posedge clk) disable iff(!rst_n)
    ($fell(re) |=> $stable(data[15:0])))
  else begin
    $display("ERROR: one or more bits of data not stable");
  end

I believe that $rose only operates on the LSB of a bus (link). Does $stable only operate on the LSB as well, or does it support signals of any width?

Upvotes: 1

Views: 5289

Answers (1)

dwikle
dwikle

Reputation: 6978

According to the spec, $stable operates on the entire expression. Whereas $rose and $fell operate on the LSB of the expression.

From section 16.9.3 of IEEE 1800-2012:

— $rose returns true if the LSB of the expression changed to 1 . Otherwise, it returns false.
— $fell returns true if the LSB of the expression changed to 0 . Otherwise, it returns false.
— $stable returns true if the value of the expression did not change. Otherwise, it returns false.
— $changed returns true if the value of the expression changed. Otherwise, it returns false.

Upvotes: 4

Related Questions