CODEWITHSUNDEEP
verilogfpgasystem-verilog
user3212932
user3212932

Reputation: 17

verilog code containing adders

i write the verilog code which contain only adders. In this g,h are 10 bits and r5(main output) is of 11 bits. When i take r5 as 11 bits then i am not getting correct output but when i take r5 as 10 bits then i am getting correct. but (r5=g+h) so its bit should be one more than bits of g,h. i took input as clk = 1;

    s189 = 10'd200;
    s375 = 10'd75;
    s050 = 10'd300;
    s218 = 10'd54;

and output should be r5= -16 but it gives output as (01111110000) instead of (11111110000)

module out(clk,s189,s375,s050,s218,r5,g,h);
input clk;
input [9:0] s189,s375,s050,s218;
output reg[10:0] r5;
output reg [9:0] g,h;
reg [3:0] countr=4'b0000;
always@(posedge clk)
begin
if (countr==4'b1000)
begin
 g<= s218-s189;
 h<= s375+s050;
 r5<=g+h;
 end
end

always@(posedge clk)
begin
 if (countr==4'b1001)
 countr<=4'b0000;
 else 
 countr<= countr+1;
end

endmodule

Upvotes: 0

Views: 189

Answers (1)

Morgan
Morgan

Reputation: 20514

You are performing unsigned arithmetic, as noted the MSB is 0 not 1 (negative) as expected. You need to declare the inputs, outputs and variables used as signed, for automatic sign extension.

module out(
  input clk, 
  input signed [9:0] s189,
  input signed [9:0] s375,
  input signed [9:0] s050,
  input signed [9:0] s218,
  output reg signed [10:0] r5,
  output reg signed [9:0] g,
  output reg signed [9:0] h
);

Upvotes: 3

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