CODEWITHSUNDEEP
makefilerule
Shuang
Shuang

Reputation: 11

how to expand variables to multiple rules in makefile?

Say that I have two variables in Makefile

CXXFILES = a.cpp b.cpp
OBJFILES = a.o b.o

I would like to write a rule that will expand to

a.cpp : a.o
  g++ -o a.o a.cpp
b.cpp : b.o
  g++ -o b.o b.cpp

Note that I'm not looking for 

%.o : %.cpp
  g++ -o $@ $<

because I don't want to match all .cpp files -- I only want those files specified by a variable.

Upvotes: 1

Views: 588

Answers (1)

etheranger
etheranger

Reputation: 1273

Sounds like a job for a Static Pattern Rule:

Here is an example, which compiles each of foo.o and bar.o from the corresponding .c file:

objects = foo.o bar.o

all: $(objects)

$(objects): %.o: %.c
    $(CC) -c $(CFLAGS) $< -o $@

Upvotes: 1

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